LT10647FB_15 Datasheet, PDF (10/16 Pages) Linear Technology – Linear Phase, 8th Order Lowpass Filter

LTC1064-7
PI FU CTIO S
Power Supply Pins (4, 12)
The V⁺ (Pin 4) and the V ^– (Pin 12) should be bypassed with
a 0.1µF capacitor to an adequate analog ground. The
filter’s power supplies should be isolated from other
digital or high voltage analog supplies. A low noise linear
supply is recommended. Using a switching power supply
will lower the signal-to-noise ratio of the filter. The supply
during power-up should have a slew rate less than 1V/µs.
When V⁺ is applied before V ^– and V ^– is allowed to go
above ground, a signal diode should clamp V ^– to prevent
latch-up. Figures 2 and 3 show typical connections for
dual and single supply operation.
V_IN
V⁺
0.1µF
V^–
1
14
2
13 _0.1µF
3
12
4 _LTC1064-7 11
5
10 _V+
6
9
200Ω
CLOCK SOURCE
7
8
GND
+
DIGITAL SUPPLY
V_OUT
1064-7 F02
Figure 2. Dual Supply Operation for an f_CLK/f_CUTOFF = 50:1
V_IN
V⁺
10k
10k
0.1µF
1
14
2
13
3
12
4 _LTC1064-7 11
5
10
6
9
7
8
+
1µF
200Ω
V⁺
CLOCK SOURCE
GND
+
DIGITAL SUPPLY
V_OUT
1064-7 F03
Figure 3. Single Supply Operation for an f_CLK/f_CUTOFF = 50:1
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
10
for the filter should be connected to clock’s ground at a
single point only. Table 7 shows the clock’s low and high
level threshold values for a dual or single supply operation.
A pulse generator can be used as a clock source provided
the high level ON time is greater than 0.1µs. Sine waves are
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤ 1µs). The clock signal should be routed from the
right side of the IC package and perpendicular to it to avoid
coupling to any input or output analog signal path. A 200Ω
resistor between clock source and pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 2 and 3).
Table 7. Clock Source High and Low Threshold Levels
POWER SUPPLY
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ± 2.5V
Single Supply = 12V
Single Suppl = 5V
HIGH LEVEL
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
LOW LEVEL
≤ 0.5V
≤ 0.5V
≤ – 2.0V
≤ 6.5V
≤ 0.5V
Analog Ground Pins (3, 5)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, Pin 3 should be connected to the analog
ground plane. For single supply operation pin 3 should be
biased at 1/2 supply and should be bypassed to the analog
ground plane with at least a 1µF capacitor (Figure 3). For
single 5V operation at the highest f_CLK of 2MHz, Pin 3
should be biased at 2V. This minimizes passband gain and
phase variations.
Ratio Input Pin (10)
The DC level at this pin determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10 at V⁺
gives a 50:1 ratio and Pin 10 at V ^– gives a 100:1 ratio. For
single supply operation the ratio is 50:1 when Pin 10 is at
V⁺ and 100:1 when Pin 10 is at ground. When Pin 10 is not
tied to ground, it should be bypassed to analog ground
10647fb