LT1056_15 Datasheet, PDF (10/16 Pages) Linear Technology – Precision, High Speed, JFET Input Operational Amplifiers

LT1055/LT1056
APPLICATIONS INFORMATION
The voltage noise spectrum is characterized by a low 1/f
corner in the 20Hz to 30Hz range, significantly lower than
on other competitive JFET input op amps. Of particular
interest is the fact that with any JFET IC amplifier, the
frequency location of the 1/f corner is proportional to the
square root of the internal gate leakage currents and,
therefore, noise doubles every 20°C. Furthermore, as
illustrated in the noise versus chip temperature curves,
the 0.1Hz to 10Hz peak-to-peak noise is a strong function
of temperature, while wideband noise (f₀ = 1kHz) is
practically unaffected by temperature.
Consequently, for optimum low frequency noise, chip
temperature should be minimized. For example, operating
an LT1056 at ±5V supplies or with a 20°C/W case-to-
ambient heat sink reduces 0.1Hz to 10Hz noise from
typically 2.5µV_P-P (±15V, free-air) to 1.5µV_P-P. Similiarly,
the noise of an LT1055 will be 1.8µV_P-P typically because
of its lower power dissipation and chip temperature.
capacitance is isolated from the “false summing” node,
and (2) it does not require a “flat top” input pulse since the
input pulse is merely used to steer current through the
diode bridges. For more details, please see Application
Note 10.
As with most high speed amplifiers, care should be
taken with supply decoupling, lead dress and component
placement.
When the feedback around the op amp is resistive (R_F), a
pole will be created with R_F, the source resistance and
capacitance (R_S, C_S), and the amplifier input capacitance
(C_IN ≈ 4pF). In low closed-loop gain configurations and
with R_S and R_F in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capacitor
(C_F) in parallel with R_F eliminates this problem. With R_S
(C_S + C_IN) = R_FC_F, the effect of the feedback pole is
completely removed.
C_F
High Speed Operation
Settling time is measured in the test circuit shown. This
test configuration has two features which eliminate prob-
lems common to settling time measurments: (1) probe
R_S
C_S
PULSE GEN
INPUT
(5V MIN STEP)
2k
50Ω
2W
2k
Settling Time Test Circuit
15V
15k
0.01 DISC
10µF
SOLID
TANTALUM
10pF (TYPICAL)
10k
–15V
0.01 DISC
15k
10µF
SOLID
TANTALUM
15V _15k
+ 10µF
SOLID
TANTALUM
0.01 DISC
–
LT1055
LT1056
+
AMPLIFIER
UNDER
TEST
AUT OUTPUT
10k
HP5082-8210
HEWLETT
PACKARD
–15V
0.01 DISC
15k
10µF
SOLID TANTALUM
= 1N4148
10
R_F
–
C_IN
+
OUTPUT
LT1055/56 AI03
15V
4.7k
15V
1/2
U440
2N160
50Ω
–15V
15V
1/2
U440
100Ω
DC ZERO
2N3866
4.7k
2N3866
3Ω
OUTPUT
TO SCOPE
3Ω
2N5160
–15V
–15V LT1055/56 AI04
10556fc