RH1084MK_15 Datasheet, PDF (1/2 Pages) Linear Technology – 5A Low Dropout Positive Adjustable Regulator

2
1
1
2
2
3
120mils × 121mils
Backside metal: Alloyed gold layer
Backside potential: substrate to Pad 2
DICE/DWF SPECIFICATION
RH1084MK
5A Low Dropout
Positive Adjustable Regulator
PAD FUNCTION
1. V_IN
2. V_OUT
3. ADJUST
DIE CROSS REFERENCE
Order DICE CANDIDATE
Part Number Below
RH1084MK DICE
RH1084MK DWF*
Please refer to LTC standard product data sheet for
other applicable product information.
*DWF = DICE in wafer form.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
DICE/DWF ELECTRICAL TEST LIMITS
PARAMETER
Reference Voltage
Line Regulation
Load Regulation
Dropout Voltage
Current Limit
Minimum Load Current
ADJUST Pin Current
ADJUST Pin Current Change
CONDITIONS
I_OUT = 10mA, (V_IN – V_OUT) = 3V
10mA ≤ I_OUT ≤ 50mA
1.5V ≤ (V_IN – V_OUT) ≤ 25V
I_OUT = 10mA, 1.5V ≤ (V_IN – V_OUT) ≤ 15V
15V ≤ (V_IN – V_OUT) ≤ 30V
(V_IN – V_OUT) = 3V
10mA ≤ I_OUT ≤ 50mA
)V_REF = 1%, I_OUT = 50mA
(V_IN – V_OUT) = 5V
(V_IN – V_OUT) = 25V
T_J = 25°C
10mA ≤ I_OUT ≤ 50mA
1.5V ≤ (V_IN – V_OUT) ≤ 25V
NOTES
1, 2
1, 2
3
MIN
1.238
1.225
5.5
MAX
1.262
1.270
0.2
0.5
0.35
1.5
10
120
5
UNITS
V
V
%
%
%
V
A
mA
µA
µA
Note 1: See the LT^®1084 data sheet thermal regulation specifications for
changes in output voltage due to heating effects. Line and load regulation
are measured at a constant junction temperature by low duty cycle pulse
testing.
Note 2: Power dissipation is determined by the input/output differential
voltage and the output current.
Note 3: Dropout voltage is tested at 50mA but guaranteed over the full
output current range of the device. Test points and limits are shown on the
Dropout Voltage curve in the LT1084 data sheet.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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