LTC2655_1 Datasheet, PDF (1/26 Pages) Linear Technology – Octal 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference

FEATURES
n _{Precision 10ppm/°C Max Reference}
n _{Maximum INL Error: ±4LSB at 16 Bits}
n _{Guaranteed Monotonic over Temperature}
n _{Selectable Internal or External Reference}
n _{2.7V to 5.5V Supply Range (LTC2656-L)}
n _{Integrated Reference Buffers}
n _{Ultralow Crosstalk Between DACs(<1nV•s)}
n _{Power-On-Reset to Zero-Scale/Mid-scale}
n _{Asynchronous LDAC Update Pin}
n _{Tiny 20-Lead 4mm × 5mm QFN and 20-Lead}
Thermally Enhanced TSSOP Packages
APPLICATIONS
n _{Mobile Communications}
n _{Process Control and Industrial Automation}
n _{Instrumentation}
n _{Automatic Test Equipment}
n _Automotive
LTC2656
Octal 16-/12-Bit Rail-to-Rail
DACs with 10ppm/°C
Max Reference
DESCRIPTION
The LTC^®2656 is a family of octal 16-/12-bit rail-to-rail
DACs with a precision integrated reference. The DACs have
built-in high performance, rail-to-rail, output buffers and
are guaranteed monotonic. The LTC2656-L has a full-scale
output of 2.5V with the integrated 10ppm/°C reference and
operates from a single 2.7V to 5.5V supply. The LTC2656-H
has a full-scale output of 4.096V with the integrated refer-
ence and operates from a 4.5V to 5.5V supply. Each DAC can
also operate with an external reference, which sets the DAC
full-scale output to two times the external reference voltage.
These DACs communicate via a SPI/MICROWIRE™ com-
patible 4-wire serial interface which operates at clock rates
up to 50MHz. The LTC2656 incorporates a power-on reset
circuit that is controlled by the PORSEL pin. If PORSEL
is tied to GND the DACs reset to zero-scale. If PORSEL is
tied to V_CC, the DACs reset to mid-scale.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5396245, 6891433.
BLOCK DIAGRAM
REFCOMP
GND
REFLO
V_OUTA
REF
DAC A
REF
INTERNAL REFERENCE
REF
DAC H
REF
REFIN/OUT
V_CC
V_OUTH
V_OUTB
DAC B
REF
DAC G
REF
V_OUTG
V_OUTC
DAC C
REF
DAC F
REF
V_OUTF
V_OUTD
CS/LD
SCK
LDAC
DAC D
CONTROL LOGIC
DECODE
32-BIT SHIFT REGISTER
DAC E
V_OUTE
POWER-ON RESET
PORSEL
SDO
SDI
CLR
2656 TA01a
4
3
2
1
0
–1
–2
–3
–4
128
INL vs Code
16384
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
32768
CODE
49152 65535
2656 TA01b
2656fa
1