LTC2635 Datasheet, PDF (1/32 Pages) Linear Technology – Mobile Communications

LTC2635
Quad 12-/10-/8-Bit I²C V_OUT
DACs with 10ppm/°C Reference
FEATURES
n _{Integrated Precision Reference}
2.5V Full-Scale 10ppm/°C (LTC2635-L)
4.096V Full-Scale 10ppm/°C (LTC2635-H)
n _{Maximum INL Error: ±2.5 LSB (LTC2635-12)}
n _{Power-On-Reset to Zero-Scale/Mid-Scale/Hi-Z}
n _{Low Noise: 0.75mVP-P 0.1Hz to 200kHz}
n _{Guaranteed Monotonic Over –40°C to 125°C}
Automotive Temperature Range
n _{Selectable Internal or External Reference}
n _{2.7V to 5.5V Supply Range (LTC2635-L)}
n _{Ultralow Crosstalk Between DACs (3nV•s)}
n _{Low Power: 0.6mA at 3V}
n _{Double-Buffered Data Latches}
n _{Small 16-Pin 3mm × 3mm QFN and 10-Lead MSOP}
Packages
APPLICATIONS
n _{Mobile Communications}
n _{Process Control and Industrial Automation}
n _{Power Supply Margining}
n _{Portable Equipment}
n _Automotive
DESCRIPTION
The LTC^®2635 is a family of quad 12-, 10-, and 8-bit
voltage-output DACs with an integrated, high-accuracy,
low-drift reference in a 16-pin QFN or a 10-lead MSOP
package. It has rail-to-rail output buffers and is guaran-
teed monotonic. The LTC2635-L has a full-scale output
of 2.5V, and operates from a single 2.7V to 5.5V supply.
The LTC2635-H has a full-scale output of 4.096V, and
operates from a 4.5V to 5.5V supply. Each DAC can also
operate with an external reference, which sets the full-
scale output to the external reference voltage.
These DACs communicate via a 2-wire I²C-compatible
serial interface. The LTC2635 operates in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). The LTC2635 incorporates a power-on reset
circuit. Options are available for reset to zero-scale, reset
to mid-scale in internal reference mode, reset to mid-scale
in external reference mode, or reset with all DAC outputs
in a high-impedance state after power-up.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5396245, 5859606, 6891433, 6937178, 7414561.
BLOCK DIAGRAM
GND
(REFLO)
V_OUTA
DAC A
V_REF
V_OUTB
DAC B
INTERNAL
REFERENCE
REF
SWITCH
V_REF
V_CC
DAC D
V_OUTD
DAC C
V_REF
V_OUTC
(LDAC)
CA0
(CA1)
(CA2)
I²C
ADDRESS
DECODE
DECODE
I²C INTERFACE
POWER-ON
RESET
SCL
SDA
Integral Nonlinerity
2
V_CC = 3V
INTERNAL REF.
1
0
–1
–2
0
1024
2048
CODE
3072
4095
2635 TA01
( ) QFN PACKAGE ONLY
2635 BD
2635f
1