LTC2633_15 Datasheet, PDF (1/24 Pages) Linear Technology – Dual 12-/10-/8-Bit I2C VOUT DACs with 10ppm/C Reference

Features
n _{Integrated Precision Reference}
2.5V Full-Scale 10ppm/°C (LTC2633-L)
4.096V Full-Scale 10ppm/°C (LTC2633-H)
n _{Maximum INL Error: ±1LSB (LTC2633A-12)}
n _{Low Noise: 0.75mVP-P 0.1Hz to 200kHz}
n _{Guaranteed Monotonic Over –40°C to 125°C}
Temperature Range
n _{Selectable Internal or External Reference}
n _{2.7V to 5.5V Supply Range (LTC2633-L)}
n _{Low Power: 0.4mA at 3V}
n _{Power-on-Reset to Zero-Scale/Mid-Scale/Hi-Z}
n _{Double-Buffered Data Latches}
n _{8-Lead ThinSOT™ Package}
Applications
n _{Mobile Communications}
n _{Process Control and Industrial Automation}
n _{Power Supply Margining}
n _{Portable Equipment}
n _Automotive
LTC2633
Dual 12-/10-/8-Bit I²C
V_OUT DACs with
10ppm/°C Reference
Description
The LTC^®2633 is a family of dual 12-, 10-, and 8-bit
voltage-output DACs with an integrated, high accuracy,
low drift reference in an 8-lead TSOT-23 package. It has
rail-to-rail output buffers and is guaranteed monotonic.
The LTC2633-L has a full-scale output of 2.5V, and operates
from a single 2.7V to 5.5V supply. The LTC2633-H has a
full-scale output of 4.096V, and operates from a 4.5V to
5.5V supply. Each DAC can also operate with an external
reference, which sets the full-scale output to the external
reference voltage.
These DACs communicate via a 2-wire I²C-compatible
serial interface. The LTC2633 operates in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). The LTC2633 incorporates a power-on reset
circuit. Options are available for reset to zero-scale, reset
to mid-scale in internal reference mode, reset to mid-scale
in external reference mode, or reset with all DAC outputs
in a high impedance state after power-up.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433,
6937178, 7414561.
Block Diagram
GND
V_CC
V_OUTA
DAC A
INTERNAL
REFERENCE
REF
SWITCH
V_REF
DAC B
V_OUTB
POWER-ON
RESET
CA0
I²C
ADDRESS
DECODE
CONTROL
DECODE LOGIC
I²C INTERFACE
SCL
SDA
2633 BD
Integral Nonlinearity (LTC2633A-LZ12)
INL Curve
2
V_CC = 3V
INTERNAL REF.
1
0
–1
–2
0
1024
2048
CODE
3072
4095
2633 TA01
2633fb
1