LTC2629_15 Datasheet, PDF (1/22 Pages) Linear Technology – Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface

Features
n _{Smallest Pin-Compatible Quad DACs:}
LTC2609: 16 Bits
LTC2619: 14 Bits
LTC2629: 12 Bits
n _{Guaranteed Monotonic Over Temperature}
n _{Separate Reference Inputs}
n _{27 Selectable Addresses}
n _{400kHz I}²_{C™ Interface}
n _{Wide 2.7V to 5.5V Supply Range}
n _{Low Power Operation: 250µA per DAC at 3V}
n _{Individual Channel Power Down to 1µA (Max)}
n _{High Rail-to-Rail Output Drive (±15mA, Min)}
n _{Ultralow Crosstalk Between DACs (5µV)}
n _{LTC2609/LTC2619/LTC2629: Power-On Reset to}
Zero-Scale
n _{LTC2609-1/LTC2619-1/LTC2629-1: Power-On Reset}
to Mid-Scale
n _{Tiny 16-Lead Narrow SSOP Package}
Applications
n _{Mobile Communications}
n _{Process Control and Industrial Automation}
n _{Automatic Test Equipment and Instrumentation}
LTC2609/LTC2619/LTC2629
Quad 16-/14-/12-Bit
Rail-to-Rail DACs with
I²C Interface
Description
The LTC^®2609/LTC2619/LTC2629 are quad 16-, 14- and 12-
bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a 16‑lead
SSOP package. They have built-in high performance output
buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply, volt-
age-output DACs.
The parts use a 2-wire, I²C compatible serial interface. The
LTC2609/LTC2619/LTC2629 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock
rate of 400kHz).
The LTC2609/LTC2619/LTC2629 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero-scale; after power-up, they stay at
zero-scale until a valid write and update take place. The
power-on reset circuit resets the LTC2609-1/LTC2619‑1/
LTC2629-1 to mid-scale. The voltage outputs stay at mid-
scale until a valid write and update take place.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245. Patent pending.
Block Diagram
REFA
3
V_OUTA
4
DAC A
2
REFLO
1
GND
16
V_CC
V_OUTB
5
REFB
6
DAC B
CONTROL
LOGIC
DAC D
REFD
15
V_OUTD
14
DAC C
V_OUTC
13
REFC
12
SCL
8
SDA
9
32-BIT SHIFT REGISTER
I²C
INTERFACE
ADDRESS
DECODE
LOGIC
CA0
11
CA1
10
CA2
7
2609 BD
Differential Nonlinearity
(LTC2609)
1.0
V_CC = 5V
0.8 V_REF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152 65535
2609 G02
26091929fb