LTC2609 Datasheet, PDF (1/20 Pages) Linear Technology – Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface

FEATURES
■ _{Smallest Pin-Compatible Quad DACs:}
LTC2609: 16 Bits
LTC2619: 14 Bits
LTC2629: 12 Bits
■ _{Guaranteed Monotonic Over Temperature}
■ _{Separate Reference Inputs}
■ _{27 Selectable Addresses}
■ _{400kHz I}²_C^™ _Interface
■ _{Wide 2.7V to 5.5V Supply Range}
■ _{Low Power Operation: 250µA per DAC at 3V}
■ _{Individual Channel Power Down to 1µA (Max)}
■ _{High Rail-to-Rail Output Drive (±15mA, Min)}
■ _{Ultralow Crosstalk Between DACs (5µV)}
■ _{LTC2609/LTC2619/LTC2629: Power-On Reset to}
Zero Scale
■ _{LTC2609-1/LTC2619-1/LTC2629-1: Power-On Reset}
to Midscale
■ _{Tiny 16-Lead Narrow SSOP Package}
U
APPLICATIO S
■ _{Mobile Communications}
■ _{Process Control and Industrial Automation}
■ _{Automatic Test Equipment and Instrumentation}
LTC2609/LTC2619/LTC2629
Quad 16-/14-/12-Bit
Rail-to-Rail DACs with
I²C Interface
DESCRIPTIO
The LTC^®2609/LTC2619/LTC2629 are quad 16-, 14- and
12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs in a
16-lead SSOP package. They have built-in high perfor-
mance output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.
The parts use a 2-wire, I²C compatible serial interface. The
LTC2609/LTC2619/LTC2629 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz).
The LTC2609/LTC2619/LTC2629 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale; after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2609-1/LTC2619-1/
LTC2629-1 to midscale. The voltage outputs stay at
midscale until a valid write and update take place.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5396245. Patent pending.
BLOCK DIAGRA
REFA 3
V_OUTA 4
DAC A
REFLO
2
V_OUTB
5
REFB 6
DAC B
GND
V_CC
1
16
CONTROL
LOGIC
DAC D
15 REFD
14 V_OUTD
DAC C
13 V_OUTC
12 REFC
SCL 8
SDA 9
32-BIT SHIFT REGISTER
I²C
INTERFACE
ADDRESS
DECODE
LOGIC
11 CA0
10 CA1
7 CA2
2609 BD
Differential Nonlinearity
(LTC2609)
1.0
V_CC = 5V
0.8 V_REF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2609 G02
26091929f
1