LTC2355-12 Datasheet, PDF (1/16 Pages) Linear Technology – Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown

LTC2355-12/LTC2355-14
Serial 12-Bit/14-Bit, 3.5Msps
Sampling ADCs with Shutdown
FEATURES
■ _{3.5Msps Conversion Rate}
■ _{74.2dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits}
■ _{Low Power Dissipation: 18mW}
■ _{3.3V Single Supply Operation}
■ _{2.5V Internal Bandgap Reference can be Overdriven}
■ _{3-Wire SPI-Compatible Serial Interface}
■ _{Sleep (13µW) Shutdown Mode}
■ _{Nap (4mW) Shutdown Mode}
■ _{80dB Common Mode Rejection}
■ _{0V to 2.5V Unipolar Input Range}
■ _{Tiny 10-Lead MSUOP Package}
APPLICATIO S
■ _{Communications}
■ _{Data Acquisition Systems}
■ _{Uninterrupted Power Supplies}
■ _{Multiphase Motor Control}
■ _{Multiplexed Data Acquisition}
■ _RFID
DESCRIPTIO
The LTC^®2355-12/LTC2355-14 are 12-bit/14-bit, 3.5Msps
serial ADCs with differential inputs. The devices draw only
5.5mA from a single 3.3V supply and come in a tiny 10-lead
MSOP package. A Sleep shutdown feature further reduces
power consumption to 13µW. The combination of speed,
low power and tiny package makes the LTC2355-12/
LTC2355-14 suitable for high speed, portable applications.
The 80dB common mode rejection allows users to elimi-
nate ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 0V to 2.5V unipolar inputs differentially.
The absolute voltage swing for A_IN+ and A_IN– extends from
ground to the supply voltage.
The serial interface sends out the conversion results during
the 16 clock cycles following a CONV rising edge for
compatibility with standard serial interfaces. If two addi-
tional clock cycles for acquisition time are allowed after the
data stream in between conversions, the full sampling rate
of 3.5Msps can be achieved with a 63MHz clock.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
BLOCK DIAGRA
10µF 3.3V
A_IN+
A_IN–
10µF
LTC2355-14
7 _VDD
1+
S&H
2–
14-BIT ADC
14
3 ^VREF
GND
4
2.5V
REFERENCE
5
6
11
EXPOSED PAD
THREE-
STATE
SERIAL
OUTPUT
PORT
8 SDO
TIMING
LOGIC
10 CONV
9 SCK
2355 TA01
THD, 2nd, 3rd and SFDR
vs Input Frequency
–50
–56
–62
THD
–68
2nd
–74
3rd
–80
–86
–92
–98
–104
–110
0.1
1
10
FREQUENCY (MHz)
100
2355 G02
2355f
1