LTC2351-12 Datasheet, PDF (1/20 Pages) Linear Technology – 6 Channel, 12-Bit, 1.5Msps Simultaneous Sampling ADC with Shutdown

FEATURES
■ _{1.5Msps ADC with 6 Simultaneously Sampled}
Differential Inputs
■ _{250ksps Throughput per Channel}
■ _{72dB SINAD}
■ _{Low Power Dissipation: 16.5mW}
■ _{3V Single Supply Operation}
■ _{2.5V Internal Bandgap Reference, Can be Overdriven}
with External Reference
■ _{3-Wire SPI-Compatible Serial Interface}
■ _{Internal Conversion Triggered by CONV}
■ _{SLEEP (12µW) Shutdown Mode}
■ _{NAP (4.5mW) Shutdown Mode}
■ _{0V to 2.5V Unipolar, or ±1.25V Bipolar Differential}
Input Range
■ _{83dB Common Mode Rejection}
■ _{Tiny 32-Pin (5mm × 5mm) QFN Package}
U
APPLICATIO S
■ _{Multiphase Power Measurement}
■ _{Multiphase Motor Control}
■ _{Data Acquisition Systems}
■ _{Uninterruptable Power Supplies}
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
LTC2351-12
6 Channel, 12-Bit, 1.5Msps
Simultaneous Sampling ADC
DESCRIPTIO ^{with Shutdown}
The LTC^®2351-12 is a 12-bit, 1.5Msps ADC with six
simultaneously sampled differential inputs. The device
draws only 5.5mA from a single 3V supply, and comes in
a tiny 32-pin (5mm × 5mm) QFN package. A SLEEP
shutdown mode further reduces power consumption to
12µW. The combination of low power and tiny package
makes the LTC2351-12 suitable for portable applications.
The LTC2351-12 contains six separate differential inputs
that are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then
converted at a rate of 250ksps per channel.
The 83dB common mode rejection allows users to
eliminate ground loops and common mode noise by
measuring signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differen-
tially, or ±1.25V bipolar inputs also differentially,
depending on the state of the BIP pin. Any analog input
may swing rail-to-rail as long as the differential input
range is maintained.
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in
96 clocks for compatibility with standard serial interfaces.
BLOCK DIAGRA
CH5^– CH5⁺
21
20 19
CH4^– CH4⁺
18
17 16
CH3^–
15
CH3⁺
14 12
13
CH2^– CH2⁺
11
10 9
CH1^– CH1⁺
8
76
CH0^– CH0⁺
5
4
–
S AND H
–
S AND H
–
S AND H
–
S AND H
–
S AND H
–
S AND H
MUX
2.5V
REFERENCE
10µF
3V
V_CC
V_DD
24
25
1.5Msps
12-BIT ADC
12-BIT LATCH 0
12-BIT LATCH 1
12-BIT LATCH 2
12-BIT LATCH 3
12-BIT LATCH 4
12-BIT LATCH 5
TIMING
LOGIC
33 22
23 29
GND ^10µF V_REF BIP
26 27 28
SEL2 SEL1 SEL0
THREE-
STATE
SERIAL
OUTPUT
PORT
OV_DD
3V
3
SD0
1
OGND
2
CONV
30
SCK
32
DGND
31
235112 TA01
0.1µF
235112f
1