LTC2274 Datasheet, PDF (1/40 Pages) Linear Technology – 16-Bit, 105Msps Serial Output ADC

FEATURES
n _{High Speed Serial Interface (JESD204)}
n _{Sample Rate: 105Msps}
n _{77.7dBFS Noise Floor}
n _{100dB SFDR}
n _{SFDR >82dB at 250MHz (1.5VP-P Input Range)}
n _{PGA Front End (2.25VP-P or 1.5VP-P Input Range)}
n _{700MHz Full Power Bandwidth S/H}
n _{Optional Internal Dither}
n _{Single 3.3V Supply}
n _{Power Dissipation: 1300mW}
n _{Clock Duty Cycle Stabilizer}
n _{Pin Compatible Family}
105Msps: LTC2274
80Msps: LTC2273
65Msps: LTC2272
n _{40-Pin 6mm × 6mm QFN Package}
APPLICATIONS
n _{Telecommunications}
n _Receivers
n _{Cellular Base Stations}
n _{Spectrum Analysis}
n _{Imaging Systems}
n _ATE
LTC2274
16-Bit, 105Msps Serial
Output ADC
DESCRIPTION
The LTC^®2274 is a 105Msps, 16-bit A/D converter with
a high speed serial interface. It is designed for digitizing
high frequency, wide dynamic range signals with an input
bandwidth of 700MHz. The input range of the ADC can
be optimized using the PGA front end. The output data is
serialized according to the JEDEC Serial Interface for Data
Converters specification (JESD204).
The LTC2274 is perfect for demanding applications where
it is desirable to isolate the sensitive analog circuits from
the noisy digital logic. The AC performance includes a
77.7dB Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low internal jitter of 80fs RMS allows under-
sampling of high input frequencies with excellent noise
performance. Maximum DC specs include ±4.5LSB INL
and ±1LSB DNL (no missing codes) over temperature.
The encode clock inputs, ENC⁺ and ENC^–, may be driven
differentially or single-ended with a sine wave, PECL,
LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer
allows high performance at full speed with a wide range
of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
V_CM
2.2μF
1.25V
COMMON MODE
BIAS VOLTAGE
3.3V
SENSE
INTERNAL ADC
REFERENCE
GENERATOR
FAM
8B/10B
ENCODER
16
20
SYNC⁺
SYNC^–
OV_DD ^{1.2V TO 3.3V}
0.1μF
A_IN ⁺
ANALOG
INPUT
A_IN ^–
CMLOUT⁺
+
S/H
AMP
–
CLOCK
16-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
CORRECTION
LOGIC
SCRAMBLER/
PATTERN
GENERATOR
SERIALIZER
CMLOUT^–
20X
PLL
3.3V
V_DD
GND
0.1μF 0.1μF
ENC⁺ ENC^– PGA DITH MSBINV SHDN
PAT1 PAT0 SCRAM SRR1 SRR0
ASIC OR FPGA
50Ω
50Ω
+
SERIAL
RECEIVER
–
2274 TA01
128k Point FFT, f_IN = 4.93MHz,
–1dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10 20 30 40 50
FREQUENCY (MHz)
2274 TA01b
2274f
1