LTC2271_15 Datasheet, PDF (1/24 Pages) Linear Technology – 16-Bit, 20Msps Serial Low Noise Dual ADC

FEATURES
n _{2-Channel Simultaneous Sampling ADC}
n _{Serial LVDS Outputs: 1, 2 or 4 Bits per Channel}
n _{84.1dB SNR (46μVRMS Input Referred Noise)}
n _{99dB SFDR}
n _{Low Power: 185mW Total}
n _{92mW per Channel}
n _{Single 1.8V Supply}
n _{Selectable Input Ranges: 1VP-P to 2.1VP-P}
n _{200MHz Full-Power Bandwidth S/H}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{Pin Compatible With}
LTC2190: 16-Bit, 25Msps, 104mW
n _{52-Lead (7mm × 8mm) QFN Package}
APPLICATIONS
n _{Low Power Instrumentation}
n _{Software-Defined Radios}
n _{Portable Medical Imaging}
n _{Multi-Channel Data Acquisition}
LTC2271
16-Bit, 20Msps
Serial Low Noise Dual ADC
DESCRIPTION
The LTC^®2271 is a 2-channel, simultaneous sampling
16-bit A/D converter designed for digitizing high frequency,
wide dynamic range signals. It is perfect for demanding
communications applications with AC performance that
includes 84.1dB SNR and 99dB spurious free dynamic
range (SFDR).
DC specs include ±1LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.44LSB_RMS.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit, two bits or
four bits at a time. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
The ENC⁺ and ENC^– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
CH1
ANALOG
S/H
INPUT
CH2
ANALOG
S/H
INPUT
ENCODE
INPUT
1.8V
V_DD
16-BIT
ADC CORE
16-BIT
ADC CORE
PLL
GND
1.8V
OV_DD
DATA
SERIALIZER
OGND
2271 TA01
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
SERIALIZED
LVDS
OUTPUTS
Integral Non-Linearity (INL)
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
16384 32768 49152 65536
OUTPUT CODE
2271 TA02
2271f
1