LTC2269 Datasheet, PDF (1/32 Pages) Linear Technology – 16-Bit, 20Msps Low Noise ADC

FEATURES
n _{84.1dB SNR (46μVRMS Input Referred Noise)}
n _{99dB SFDR}
n _{±2.3LSB INL(Maximum)}
n _{Low Power: 88mW}
n _{Single 1.8V Supply}
n _{CMOS, DDR CMOS, or DDR LVDS Outputs}
n _{Selectable Input Ranges: 1VP-P to 2.1VP-P}
n _{200MHz Full Power Bandwidth S/H}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{Pin Compatible with}
LTC2160:16-Bit, 25Msps, 45mW
n _{48-Lead (7mm × 7mm) QFN Package}
APPLICATIONS
n _{Low Power Instrumentation}
n _{Software Defined Radios}
n _{Portable Medical Imaging}
n _{Multichannel Data Acquisition}
LTC2269
16-Bit, 20Msps
Low Noise ADC
DESCRIPTION
The LTC^®2269 is a sampling 16-bit A/D converter designed
for digitizing high frequency, wide dynamic range signals.
It is perfect for demanding communications applications
with AC performance that includes 84.1dB SNR and 99dB
spurious free dynamic range (SFDR).
DC specs include ±1LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.44LSB_RMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
V_DD
ANALOG
INPUT
S/H
16-BIT
ADC CORE
20MHz
CLOCK
2269 TA01
CLOCK
CONTROL
GND
1.8V
OV_DD
OUTPUT
DRIVERS
OGND
D15
t CMOS
t DDR CMOS OR
t ^{DDR LVDS}
D0 ^OUTPUTS
Integral Non-Linearity (INL)
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
16384 32768 49152 65536
OUTPUT CODE
2269 TA02
2269f
1