LTC2222_15 Datasheet, PDF (1/28 Pages) Linear Technology – 12-Bit,105Msps/ 80Msps ADCs

FEATURES
n _{Sample Rate: 105Msps/80Msps}
n _{68dB SNR up to 140MHz Input}
n _{80dB SFDR up to 170MHz Input}
n _{775MHz Full Power Bandwidth S/H}
n _{Single 3.3V Supply}
n _{Low Power Dissipation: 475mW/366mW}
n _{Selectable Input Ranges: ±0.5V or ±1V}
n _{No Missing Codes}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Shutdown and Nap Modes}
n _{Data Ready Output Clock}
n _{Pin Compatible Family}
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
n _{48-Pin QFN Package}
APPLICATIONS
n _{Wireless and Wired Broadband Communication}
n _{Cable Head-End Systems}
n _{Power Amplifier Linearization}
n _{Communications Test Equipment}
LTC2222/LTC2223
12-Bit,105Msps/
80Msps ADCs
DESCRIPTION
The LTC^®2222 and LTC2223 are 105Msps/80Msps, sam-
pling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2222/
LTC2223 are perfect for demanding communications
applications with AC performance that includes 68dB
SNR and 80dB spurious free dynamic range for signals
up to 170MHz. Ultralow jitter of 0.15ps_RMS allows
undersampling of IF frequencies with excellent noise
performance.
DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB_RMS.
A separate output power supply allows the outputs to
drive 0.5V to 3.6V logic.
The ENC⁺ and ENC^– inputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
V_DD
3.3V
REFH
REFL
FLEXIBLE
REFERENCE
ANALOG
INPUT
+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
OUTPUT
DRIVERS
0V_DD
0.5V TO 3.6V
D11
•
•
•
D0
0GND
22223 TA01
100
95
90
85
80
75
70
65
60
0
SFDR vs Input Frequency
4th OR HIGHER
2nd or 3rd
100 200 300 400 500 600
INPUT FREQUENCY (MHz)
22223 TA01b
22223fb
1