LTC2220-1 Datasheet, PDF (1/28 Pages) Linear Technology – 12-Bit,185Msps ADC

LTC2220-1
12-Bit,185Msps ADC
FEATURES
■ _{Sample Rate: 185Msps}
■ _{67.5dB SNR up to 140MHz Input}
■ _{80dB SFDR up to 170MHz Input}
■ _{775MHz Full Power Bandwidth S/H}
■ _{Single 3.3V Supply}
■ _{Low Power Dissipation: 910mW}
■ _{LVDS, CMOS, or Demultiplexed CMOS Outputs}
■ _{Selectable Input Ranges: ±0.5V or ±1V}
■ _{No Missing Codes}
■ _{Optional Clock Duty Cycle Stabilizer}
■ _{Shutdown and Nap Modes}
■ _{Data Ready Output Clock}
■ _{Pin Compatible Family}
185Msps: LTC2220-1 (12-Bit)
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
■ _{64-Pin 9mm × 9mm QFN Package}
U
APPLICATIO S
■ _{Wireless and Wired Broadband Communication}
■ _{Cable Head-End Systems}
■ _{Power Amplifier Linearization}
■ _{Communications Test Equipment}
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
DESCRIPTIO
The LTC^®2220-1 is a 185Msps, sampling 12-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2220-1 is perfect for
demanding communications applications with AC perfor-
mance that includes 67.5dB SNR and 80dB spurious free
dynamic range for signals up to 170MHz. Ultralow jitter of
0.15ps_RMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.7LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB_RMS.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC⁺ and ENC^– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
3.3V
V_DD
ANALOG
INPUT
+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
OUTPUT
DRIVERS
0.5V
TO 3.6V
OV_DD
D11
• CMOS
• OR
• LVDS
D0
OGND
22201 TA01
SFDR vs Input Frequency
100
90
4th OR HIGHER
80
70
2nd OR 3rd
60
50
40
0 100 200 300 400 500 600
INPUT FREQUENCY (MHz)
22201 TA01b
2220_1fa
1