LTC2217 Datasheet, PDF (1/32 Pages) Linear Technology – 16-Bit, 105Msps Low Noise ADC

FEATURES
■ _{Sample Rate: 105Msps}
■ _{81.3dBFS Noise Floor}
■ _{100dB SFDR}
■ _{SFDR >90dB at 70MHz}
■ _{85fsRMS Jitter}
■ _{2.75VP-P Input Range}
■ _{400MHz Full Power Bandwidth S/H}
■ _{Optional Internal Dither}
■ _{Optional Data Output Randomizer}
■ _{LVDS or CMOS Outputs}
■ _{Single 3.3V Supply}
■ _{Power Dissipation: 1.19W}
■ _{Clock Duty Cycle Stabilizer}
■ _{Pin Compatible with LTC2208}
■ _{64-Pin (9mm × 9mm) QFN Package}
APPLICATIONS
■ _{Telecommunications}
■ _Receivers
■ _{Cellular Base Stations}
■ _{Spectrum Analysis}
■ _{Imaging Systems}
■ _ATE
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patents Pending.
LTC2217
16-Bit, 105Msps
Low Noise ADC
DESCRIPTION
The LTC^®2217 is a 105Msps sampling 16-bit A/D converter
designed for digitizing high frequency, wide dynamic range
signals with input frequencies up to 400MHz. The input
range of the ADC is fixed at 2.75V_P-P.
The LTC2217 is perfect for demanding communications
applications, with AC performance that includes 81.3dBFS
Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low jitter of 85fs_RMS allows undersampling
of high input frequencies while maintaining excellent noise
performance. Maximum DC specifications include ±3.5LSB
INL, ±1LSB DNL (no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
TYPICAL APPLICATION
V_CM
2.2μF
1.575V
COMMON MODE
BIAS VOLTAGE
3.3V
SENSE
INTERNAL ADC
REFERENCE
GENERATOR
OV_DD
AIN⁺
ANALOG
INPUT
AIN^–
+
S/H
AMP
–
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
CLOCK/DUTY
CYCLE
CONTROL
ENC ⁺ ENC ^–
OGND
V_DD
GND
SHDN DITH MODE LVDS RAND
ADC CONTROL INPUTS
0.5V TO 3.6V
1μF
OF
CLKOUT
D15
•
•
•
D0
CMOS
OR
LVDS
1μF
1μF
3.3V
1μF
2217 TA01
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
64k Point FFT,
F_IN = 4.9MHz, –1dBFS
10 20 30 40
FREQUENCY (MHz)
50
2217 TA01b
2217f
1