LTC2209 Datasheet, PDF (1/32 Pages) Linear Technology – 16-Bit, 160Msps ADC

FEATURES
n _{Sample Rate: 160Msps}
n _{77.3dBFS Noise Floor}
n _{100dB SFDR}
n _{SFDR >84dB at 250MHz (1.5VP-P Input Range)}
n _{PGA Front End (2.25VP-P or 1.5VP-P Input Range)}
n _{700MHz Full Power Bandwidth S/H}
n _{Optional Internal Dither}
n _{Optional Data Output Randomizer}
n _{LVDS or CMOS Outputs}
n _{Single 3.3V Supply}
n _{Power Dissipation: 1.45W}
n _{Clock Duty Cycle Stabilizer}
n _{Pin-Compatible Family:}
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)
105Msps: LTC2217 (16-Bit)
n _{64-Pin (9mm × 9mm) QFN Package}
APPLICATIONS
n _{Telecommunications}
n _Receivers
n _{Cellular Base Stations}
n _{Spectrum Analysis}
n _{Imaging Systems}
n _ATE
LTC2209
16-Bit, 160Msps ADC
DESCRIPTION
The LTC^®2209 is a 160Msps 16-bit A/D converter designed
for digitizing high frequency, wide dynamic range signals
with input frequencies up to 700MHz. The input range of
the ADC can be optimized with the PGA front end.
The LTC2209 is perfect for demanding communications
applications, with AC performance that includes 77.3dBFS
Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low jitter of 70fs_RMS allows undersampling
of high input frequencies with excellent noise performance.
Maximum DC specs include ±5LSB INL, ±1LSB DNL (no
missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for
the CMOS outputs: a single bus running at the full data
rate or demultiplexed busses running at half data rate. A
separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
V_CM
2.2μF
1.25V
COMMON MODE
BIAS VOLTAGE
AIN⁺
ANALOG
INPUT
AIN^–
+
S/H
AMP
–
CLOCK/DUTY
CYCLE
CONTROL
ENC ⁺ ENC ^–
3.3V
SENSE
INTERNAL ADC
REFERENCE
GENERATOR
OV_DD
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
OGND
V_DD
GND
PGA SHDN DITH MODE LVDS RAND
ADC CONTROL INPUTS
0.5V TO 3.6V
1μF
OF
CLKOUT
D15
•
•
•
D0
CMOS
OR
LVDS
1μF
1μF
3.3V
1μF
2209 TA01
64k Point FFT, f_IN = 15.1MHz,
–1dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
2209 TA01b
2209fa
1