LTC2208_15 Datasheet, PDF (1/32 Pages) Linear Technology – 16-Bit, 130Msps ADC

FEATURES
n _{Sample Rate: 130Msps}
n _{78dBFS Noise Floor}
n _{100dB SFDR}
n _{SFDR >83dB at 250MHz (1.5VP-P Input Range)}
n _{PGA Front End (2.25VP-P or 1.5VP-P Input Range)}
n _{700MHz Full Power Bandwidth S/H}
n _{Optional Internal Dither}
n _{Optional Data Output Randomizer}
n _{LVDS or CMOS Outputs}
n _{Single 3.3V Supply}
n _{Power Dissipation: 1.25W}
n _{Clock Duty Cycle Stabilizer}
n _{Pin Compatible 14-Bit Version}
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)
n _{64-Pin (9mm × 9mm) QFN Package}
APPLICATIONS
n _{Telecommunications}
n _Receivers
n _{Cellular Base Stations}
n _{Spectrum Analysis}
n _{Imaging Systems}
n _ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2208
16-Bit, 130Msps ADC
DESCRIPTION
The LTC^®2208 is a 130Msps, sampling 16-bit A/D converter
designed for digitizing high frequency, wide dynamic
range signals with input frequencies up to 700MHz. The
input range of the ADC can be optimized with the PGA
front end.
The LTC2208 is perfect for demanding communications
applications, with AC performance that includes 78dBFS
Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low jitter of 70fs_RMS allows undersampling
of high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
TYPICAL APPLICATION
V_CM
2.2μF
1.25V
COMMON MODE
BIAS VOLTAGE
3.3V
SENSE
INTERNAL ADC
REFERENCE
GENERATOR
OV_DD
AIN⁺
ANALOG
INPUT
AIN^–
+
S/H
AMP
–
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
CLOCK/DUTY
CYCLE
CONTROL
ENC ⁺ ENC ^–
OGND
V_DD
GND
PGA SHDN DITH MODE LVDS RAND
ADC CONTROL INPUTS
0.5V TO 3.6V
1μF
OF
CLKOUT
D15
•
•
•
D0
CMOS
OR
LVDS
1μF
1μF
3.3V
1μF
2208 TA01
64k Point FFT, F_IN = 15.1MHz,
–1dB, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10 20 30 40 50 60
FREQUENCY (MHz)
2208 TA01b
2208fc
1