LTC2205 Datasheet, PDF (1/36 Pages) Linear Technology – 16-Bit, 65Msps/40Msps

FEATURES
n _{Sample Rate: 65Msps/40Msps}
n _{79dB SNR and 100dB SFDR (2.25VP-P Range)}
n _{SFDR >92dB at 140MHz (1.5VP-P Input Range)}
n _{PGA Front End (2.25VP-P or 1.5VP-P Input Range)}
n _{700MHz Full Power Bandwidth S/H}
n _{Optional Internal Dither}
n _{Optional Data Output Randomizer}
n _{Single 3.3V Supply}
n _{Power Dissipation: 610mW/480mW}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Out-of-Range Indicator}
n _{Pin Compatible Family}
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
40Msps: LTC2204 (16-Bit)
n _{48-Pin (7mm × 7mm) QFN Package}
U
APPLICATIO S
n _{Telecommunications}
n _Receivers
n _{Cellular Base Stations}
n _{Spectrum Analysis}
n _{Imaging Systems}
n _ATE
LTC2205/LTC2204
16-Bit, 65Msps/40Msps
ADCs
DESCRIPTIO
The LTC^®2205/LTC2204 are sampling 16-bit A/D converters
designed for digitizing high frequency, wide dynamic range
signals up to input frequencies of 700MHz. The input range
of the ADC can be optimized with the PGA front end.
The LTC2205/LTC2204 are perfect for demanding com-
munications applications, with AC performance that in-
cludes 79dB SNR and 100dB spurious free dynamic range
(SFDR). Ultralow jitter of 90fs_RMS allows undersampling of
high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes).
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
V_CM
2.2µF
1.25V
COMMON MODE
BIAS VOLTAGE
3.3V
SENSE
INTERNAL ADC
REFERENCE
GENERATOR
OV_DD
AIN⁺
ANALOG
INPUT
AIN^–
+
S/H
AMP
–
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
CLOCK/DUTY
CYCLE
CONTROL
ENC ENC
OGND
V_DD
GND
PGA SHDN DITH MODE OE
ADC CONTROL INPUTS
RAND
0.5V TO 3.6V
0.1µF
OF
CLKOUT
D15
•
•
•
D0
0.1µF
0.1µF
3.3V
0.1µF
22076 TA01
LTC2205: 64K Point FFT,
f_IN = 5.1MHz, –1dBFS,
PGA = 0, DITH = 0
0
–20
–40
–60
–80
–100
–120
–140
0
5 10 15 20 25 30
FREQUENCY (MHz)
22054 TA01b
22054fb
1