LTC2205-14 Datasheet, PDF (1/28 Pages) Linear Technology – 14-Bit, 65Msps ADC

LTC2205-14
14-Bit, 65Msps ADC
FEATURES
■ _{Sample Rate: 65Msps}
■ _{78.3dB SNR and 98dB SFDR (2.25VP-P Range)}
■ _{SFDR >90dB at 140MHz (1.5VP-P Input Range)}
■ _{PGA Front End (2.25VP-P or 1.5VP-P Input Range)}
■ _{700MHz Full Power Bandwidth S/H}
■ _{Optional Internal Dither}
■ _{Optional Data Output Randomizer}
■ _{Single 3.3V Supply}
■ _{Power Dissipation: 600mW}
■ _{Optional Clock Duty Cycle Stabilizer}
■ _{Out-of-Range Indicator}
■ _{Pin Compatible Family}
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit)
40Msps: LTC2204 (16-Bit)
■ _{48-Pin (7mm × 7mm) QFN Package}
U
APPLICATIO S
■ _{Telecommunications}
■ _Receivers
■ _{Cellular Base Stations}
■ _{Spectrum Analysis}
■ _{Imaging Systems}
■ _ATE
DESCRIPTIO
The LTC^®2205-14 is a sampling 14-bit A/D converter de-
signed for digitizing high frequency, wide dynamic range
signals up to input frequencies of 700MHz. The input range
of the ADC can be optimized with the PGA front end.
The LTC2205-14 is perfect for demanding communications
applications, with AC performance that includes 78.3dB
SNR and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 90fs_RMS allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±1LSB DNL
(no missing codes).
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
3.3V
SENSE
V_CM
2.2µF
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
AIN⁺
ANALOG
INPUT
AIN^–
+
S/H
AMP
–
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OV_DD
OUTPUT
DRIVERS
CLOCK/DUTY
CYCLE
CONTROL
ENC ENC
OGND
V_DD
GND
PGA SHDN DITH MODE OE
ADC CONTROL INPUTS
RAND
0.5V TO 3.6V
0.1µF
OF
CLKOUT
D13
•
•
•
D0
0.1µF
0.1µF
3.3V
0.1µF
220514 TA01
LTC2205-14: 32K Point FFT,
f_IN = 5.1MHz, –1dBFS,
PGA = 0, DITH = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
5 10 15 20 25 30
FREQUENCY (MHz)
220514 G04
220514fa
1