LTC2190_15 Datasheet, PDF (1/28 Pages) Linear Technology – 16-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs

FEATURES
n _{2-Channel Simultaneous Sampling ADC}
n _{Serial LVDS Outputs: 1, 2 or 4 Bits per Channel}
n _{77dB SNR}
n _{90dB SFDR}
n _{Low Power: 198mW/146mW/104mW Total}
n _{99mW/73mW/52mW per Channel}
n _{Single 1.8V Supply}
n _{Selectable Input Ranges: 1VP-P to 2VP-P}
n _{550MHz Full-Power Bandwidth S/H}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{52-Pin (7mm × 8mm) QFN Package}
APPLICATIONS
n _{Communications}
n _{Cellular Base Stations}
n _{Software-Defined Radios}
n _{Portable Medical Imaging}
n _{Multi-Channel Data Acquisition}
n _{Nondestructive Testing}
LTC2192
LTC2191/LTC2190
16-Bit, 65Msps/40Msps/
25Msps Low Power
Dual ADCs
DESCRIPTION
The LTC^®2192/LTC2191/LTC2190 are 2-channel, simul-
taneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 77dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.07ps_RMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.3LSB_RMS.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit, two bits or
four bits at a time. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
The ENC⁺ and ENC^– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
CH1
ANALOG
S/H
INPUT
CH2
ANALOG
S/H
INPUT
ENCODE
INPUT
1.8V
V_DD
16-BIT
ADC CORE
16-BIT
ADC CORE
PLL
GND
1.8V
OV_DD
DATA
SERIALIZER
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
SERIALIZED
LVDS
OUTPUTS
OGND
219210 TA01a
2-Tone FFT, f_IN = 70MHz and 69MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
FREQUENCY (MHz)
30
219210 G07
219210f
1