LTC2181_15 Datasheet, PDF (1/36 Pages) Linear Technology – 16-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs

FEATURES
n _{Two-Channel Simultaneously Sampling ADC}
n _{77dB SNR}
n _{90dB SFDR}
n _{Low Power: 160mW/115mW/78mW Total}
80mW/58mW/39mW per Channel
n _{Single 1.8V Supply}
n _{CMOS, DDR CMOS, or DDR LVDS Outputs}
n _{Selectable Input Ranges: 1VP-P to 2VP-P}
n _{550MHz Full Power Bandwidth S/H}
n _{Optional Data Output Randomizer}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{64-Pin (9mm × 9mm) QFN Package}
APPLICATIONS
n _{Communications}
n _{Cellular Base Stations}
n _{Software Defined Radios}
n _{Portable Medical Imaging}
n _{Multi-Channel Data Acquisition}
n _{Nondestructive Testing}
LTC2182/LTC2181/LTC2180
16-Bit, 65Msps/
40Msps/25Msps Low Power
Dual ADCs
DESCRIPTION
The LTC^®2182/LTC2181/LTC2180 are two-channel si-
multaneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 77dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.07ps_RMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.3LSB_RMS.
The digital outputs can be either full rate CMOS, Double
Data Rate CMOS, or Double Data Rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
V_DD
CH 1
ANALOG
S/H
INPUT
16-BIT
ADC CORE
CH 2
ANALOG
INPUT
65MHz
CLOCK
S/H
16-BIT
ADC CORE
CLOCK
CONTROL
GND
1.8V
OV_DD
OUTPUT
DRIVERS
D1_15
•
•
•
D1_0
D2_15
•
•
•
D2_0
CMOS,
DDR CMOS
OR DDR LVDS
OUTPUTS
OGND
218210 TA01a
2-Tone FFT, f_IN = 70MHz and 69MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
FREQUENCY (MHz)
30
218210 TA01b
218210f
1