LTC2161_15 Datasheet, PDF (1/36 Pages) Linear Technology – 16-Bit, 65Msps/ 40Msps/25Msps Low Power ADCs

Features
n _{77dB SNR}
n _{90dB SFDR}
n _{Low Power: 87mW/63mW/45mW}
n _{Single 1.8V Supply}
n _{CMOS, DDR CMOS, or DDR LVDS Outputs}
n _{Selectable Input Ranges: 1VP-P to 2VP-P}
n _{550MHz Full Power Bandwidth S/H}
n _{Optional Data Output Randomizer}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{48-Pin (7mm × 7mm) QFN Package}
Applications
n _{Communications}
n _{Cellular Base Stations}
n _{Software Defined Radios}
n _{Portable Medical Imaging}
n _{Multichannel Data Acquisition}
n _{Nondestructive Testing}
LTC2162/LTC2161/LTC2160
16-Bit, 65Msps/
40Msps/25Msps
Low Power ADCs
Description
The LTC^®2162/LTC2161/LTC2160 are sampling 16-bit A/D
converters designed for digitizing high frequency, wide
dynamic range signals. They are perfect for demanding
communications applications with AC performance that
includes 77dB SNR and 90dB spurious free dynamic range
(SFDR). Ultralow jitter of 0.07ps_RMS allows undersampling
of IF frequencies with excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.3LSB_RMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
1.8V
V_DD
ANALOG
INPUT
S/H
16-BIT
ADC CORE
125MHz
CLOCK
216210 TA01a
CLOCK
CONTROL
GND
1.8V
OV_DD
OUTPUT
DRIVERS
OGND
D15
• CMOS
• DDR CMOS OR
• ^{DDR LVDS}
D0 ^OUTPUTS
2-Tone FFT, f_IN = 70MHz and 69MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
FREQUENCY (MHz)
30
2162 TA01b
216210f
1