LTC2153-12_15 Datasheet, PDF (1/24 Pages) Linear Technology – 12-Bit 310Msps ADC

Features
n _{67.6dBFS SNR}
n _{88dB SFDR}
n _{Low Power: 378mW Total}
n _{Single 1.8V Supply}
n _{DDR LVDS Outputs}
n _{1.32VP-P Input Range}
n _{1.25GHz Full Power Bandwidth S/H}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Low Power Sleep and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{Pin-Compatible 12-Bit Versions}
n _{40-Lead (6mm × 6mm) QFN Package}
Applications
n _{Communications}
n _{Cellular Basestations}
n _{Software Defined Radios}
n _{Medical Imaging}
n _{High Definition Video}
n _{Testing and Measurement Instruments}
LTC2153-12
12-Bit 310Msps ADC
Description
The LTC^®2153-12 is a 310Msps 12-bit A/D converter
designed for digitizing high frequency, wide dynamic
range signals. It is perfect for demanding communications
applications with AC performance that includes 67.6dB
SNR and 88dB spurious free dynamic range (SFDR). The
1.25GHz input bandwidth allows the ADC to undersample
high frequencies with good performance. The latency is
only six clock cycles.
DC specs include ±0.6LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.6LSB_RMS.
The digital outputs are double data rate (DDR) LVDS.
The ENC⁺ and ENC^– inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
ANALOG
INPUT
S/H
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
V_DD
12-BIT
PIPELINED
ADC
CORRECTION
LOGIC
GND
OUTPUT
DRIVERS
OV_DD
D10_11
•
•
•
D0_1
DDR
LVDS
OGND
215312 TA01a
LTC2153-12 32K Point 2-Tone FFT,
f_IN = 71MHz and 69MHz, 310Msps
0
–20
–40
–60
–80
–100
–120
0 20 40 60 80 100 120 140
FREQUENCY (MHz)
215312 TA01b
For more information www.linear.com/LTC2153-12
215312fa
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