LTC2152-14 Datasheet, PDF (1/32 Pages) Linear Technology – 14-Bit 250Msps/ 210Msps/170Msps ADCs

FEATURES
n _{70dB SNR}
n _{90dB SFDR}
n _{Low Power: 338mW/316mW/290mW Total}
n _{Single 1.8V Supply}
n _{DDR LVDS Outputs}
n _{Easy-to-Drive 1.5VP-P Input Range}
n _{1.25GHz Full Power Bandwidth S/H}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Low Power Sleep and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{Pin Compatible with 12-Bit Versions}
n _{40-Pin (6mm × 6mm) QFN Package}
APPLICATIONS
n _{Communications}
n _{Cellular Basestations}
n _{Software Defined Radios}
n _{Medical Imaging}
n _{High Definition Video}
n _{Testing and Measurement Instruments}
Electrical Specifications Subject to Change
LTC2152-14/
LTC2151-14/LTC2150-14
14-Bit 250Msps/
210Msps/170Msps ADCs
DESCRIPTION
The LTC^®2152-14/LTC2151-14/LTC2150-14 are 250Msps/
210Msps/170Msps 14-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 70dB SNR and 90dB
spurious free dynamic range (SFDR). The latency is only
five clock cycles.
DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.82LSB_RMS.
The digital outputs are Double-Data Rate (DDR) LVDS.
The ENC⁺ and ENC^– inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
ANALOG
INPUT
S/H
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
V_DD
14-BIT
PIPELINED
ADC
CORRECTION
LOGIC
OUTPUT
DRIVERS
OV_DD
D12_13
•
•
•
D0_1
DDR
LVDS
OGND
21521014 TA01a
32K Point FFT,
f_IN = 15MHz, –1dBFS, 250Msps
0
–20
–40
–60
–80
–100
–120
0
20 40 60 80 100 120
FREQUENCY (MHz)
21521014 TA01b
21521014p
1