LTC2141-12_15 Datasheet, PDF (1/38 Pages) Linear Technology – 12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs

FEATURES
n _{2-Channel Simultaneously Sampling ADC}
n _{70.8dB SNR}
n _{89dB SFDR}
n _{Low Power: 92mW/65mW/48mW Total}
46mW/33mW/24mW per Channel
n _{Single 1.8V Supply}
n _{CMOS, DDR CMOS, or DDR LVDS Outputs}
n _{Selectable Input Ranges: 1VP-P to 2VP-P}
n _{750MHz Full Power Bandwidth S/H}
n _{Optional Data Output Randomizer}
n _{Optional Clock Duty Cycle Stabilizer}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{64-Pin (9mm × 9mm) QFN Package}
APPLICATIONS
n _{Communications}
n _{Cellular Base Stations}
n _{Software Defined Radios}
n _{Portable Medical Imaging}
n _{Multi-Channel Data Acquisition}
n _{Nondestructive Testing}
LTC2142-12/
LTC2141-12/LTC2140-12
12-Bit, 65Msps/
40Msps/25Msps Low Power
Dual ADCs
DESCRIPTION
The LTC^®2142-12/LTC2141-12/LTC2140-12 are 2-channel
simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.8dB SNR and
89dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.08ps_RMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 0.3LSB_RMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
V_DD
CH 1
ANALOG
S/H
INPUT
12-BIT
ADC CORE
CH 2
ANALOG
INPUT
65MHz
CLOCK
S/H
12-BIT
ADC CORE
CLOCK
CONTROL
GND
1.8V
OV_DD
OUTPUT
DRIVERS
D1_11
t
t
t
D1_0
D2_11
t
t
t
D2_0
CMOS,
DDR CMOS
OR
DDR LVDS
OUTPUTS
OGND
21421012 TA01a
2-Tone FFT, f_IN = 70MHz and 69MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
FREQUENCY (MHz)
30
21821012 TA01b
21421012fa
1