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LTC1852_15 Datasheet, PDF (1/24 Pages) Linear Technology – 8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs | |||
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LTC1852/LTC1853
8-Channel, 10-Bit/12-Bit,
400ksps, Low Power, Sampling ADCs
FEATURES
n Flexible 8-Channel Multiplexer
Single-Ended or Differential Inputs
Two Gain Ranges
Unipolar or Bipolar Operation
n Scan Mode and Programmable Sequencer
Eliminate Conï¬guration Software Overhead
n Low Power: 3mW at 250ksps
n 2.7V to 5.5V Supply Range
n Internal or External Reference Operation
n Parallel Output Includes MUX Address
n Nap and Sleep Shutdown Modes
n Pin Compatible up-grade 1.25Msps 10-Bit LTC1850
and 12-Bit LTC1851
APPLICATIONS
n High Speed Data Acquisition
n Test and Measurement
n Imaging Systems
n Telecommunications
n Industrial Process Control
n Spectrum Analysis
DESCRIPTION
The 10-bit LTC®1852 and 12-bit LTC1853 are complete
8-channel data acquisition systems. They include a ï¬exible
8-channel multiplexer, a 400ksps successive approxima-
tion analog-to-digital converter, an internal reference and a
parallel output interface. The multiplexer can be conï¬gured
for single-ended or differential inputs, two gain ranges and
unipolar or bipolar operation. The ADCs have a scan mode
that will repeatedly cycle through all 8 multiplexer channels
and can also be programmed to sequence through up to
16 addresses and conï¬gurations. The sequence can also
be read back from internal memory.
The reference and buffer ampliï¬er provide pin strappable
ranges of 4.096V, 2.5V and 2.048V. The parallel output
includes the 10-bit or 12-bit conversion result plus the
4-bit multiplexer address. The digital outputs are pow-
ered from a separate supply allowing for easy interface
to 3V digital logic. Typical power consumption is 10mW
at 400ksps from a single 5V supply and 3mW at 250ksps
from a single 3V supply.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRAM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
REFOUT
8-CHANNEL
MULTIPLEXER
2.5V
REFERENCE
LTC1853
INTERNAL
CLOCK
+ 12-BIT
â
SAMPLING
ADC
REFIN
REF AMP
REFCOMP
CONTROL LOGIC
AND
PROGRAMMABLE
SEQUENCER
DATA
LATCHES
OUTPUT
DRIVERS
M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
OVDD
BUSY
DIFFOUT/S6
A2OUT/S5
A1OUT/S4
A0OUT/S3
D11/S2
D10/S1
D9/S0
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
18523 BD
Integral Linearity
1.0
0.5
0
â0.5
â1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
1852 F01
18523fa
1
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