LTC1749 Datasheet, PDF (1/20 Pages) Linear Technology – 12-Bit, 80Msps Wide Bandwidth ADC

FEATURES
s _{Sample Rate: 80Msps}
s _{PGA Front End (2.25VP-P or 1.35VP-P Input Range)}
s _{71.8dB SNR and 87dB SFDR (PGA = 0)}
s _{70.2dB SNR and 87dB SFDR (PGA = 1)}
s _{500MHz Full Power Bandwidth S/H}
s _{No Missing Codes}
s _{Single 5V Supply}
s _{Power Dissipation: 1.45W}
s _{Two Pin Selectable Reference Values}
s _{Data Ready Output Clock}
s _{Pin Compatible 14-Bit 80Msps Device (LTC1750)}
s _{48-Pin TSSOP Package}
U
APPLICATIO S
s _{Direct IF Sampling}
s _{Telecommunications}
s _Receivers
s _{Cellular Base Stations}
s _{Spectrum Analysis}
s _{Communications Test Equipment}
s _{Undersampling}
LTC1749
12-Bit, 80Msps
Wide Bandwidth ADC
DESCRIPTIO
The LTC^®1749 is an 80Msps, 12-bit A/D converter de-
signed for digitizing wide dynamic range signals up to
frequencies of 500MHz. The input range of the ADC can be
optimized with the on-chip PGA sample-and-hold circuit
and flexible reference circuitry.
The LTC1749 has a highly linear sample-and-hold circuit
with a bandwidth of 500MHz. The SFDR is 80dB with an
input frequency of 250MHz. Ultralow jitter of 0.15ps_RMS
allows undersampling of IF frequencies with minimal
degradation in SNR. DC specs include ±1LSB INL and no
missing codes.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic systems. The ENC and ENC inputs may be
driven differentially from PECL, GTL and other low swing
logic families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to low voltage
DSPs or FIFOs.
The 48-pin TSSOP package with a flow-through pinout
simplifies the board layout.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
PGA
A_IN+
±1.125V
DIFFERENTIAL
ANALOG INPUT AIN–
SENSE
RANGE
SELECT
V_CM
4.7µF
2V_REF
80Msps, 12-Bit ADC with a 2.25V Differential Input Range
S/H
CIRCUIT
12-BIT
PIPELINED ADC
BUFFER
DIFF AMP
CORRECTION
LOGIC AND
12
OUTPUT
SHIFT
LATCHES
REGISTER
OV_DD
0.1µF
•••
D11
D0
CLKOUT
OGND
V_DD
1µF
1µF
0.5V TO 5V
0.1µF
5V
1µF
GND
CONTROL LOGIC
REFLB
0.1µF
1µF
REFHA
4.7µF
REFLA REFHB
ENC ENC MSBINV
0.1µF
1µF
DIFFERENTIAL
ENCODE INPUT
1749 BD
1749f
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