LTC1744_15 Datasheet, PDF (1/24 Pages) Linear Technology – 14-Bit, 50Msps ADC

FEATURES
s _{Sample Rate: 50Msps}
s _{77dB SNR and 87dB SFDR (3.2V Range)}
s _{73.5dB SNR and 90dB SFDR (2V Range)}
s _{No Missing Codes}
s _{Single 5V Supply}
s _{Power Dissipation: 1.2W}
s _{Selectable Input Ranges: ±1V or ±1.6V}
s _{150MHz Full Power Bandwidth S/H}
s _{Pin Compatible Family}
25Msps: LTC1746 (14 Bit), LTC1745 (12 Bit)
50Msps: LTC1744 (14 Bit), LTC1743 (12 Bit)
65Msps: LTC1742 (14 Bit), LTC1741 (12 Bit)
80Msps: LTC1748 (14 Bit), LTC1747 (12 Bit)
s _{48-Pin TSSOP Package}
U
APPLICATIO S
s _{Telecommunications}
s _Receivers
s _{Base Stations}
s _{Spectrum Analysis}
s _{Imaging Systems}
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC1744
14-Bit, 50Msps ADC
DESCRIPTIO
The LTC^®1744 is a 50Msps, sampling 14-bit A/D con-
verter designed for digitizing high frequency, wide dynamic
range signals. Pin selectable input ranges of ±1V and ±1.6V
along with a resistor programmable mode allow the
LTC1744’s input range to be optimized for a wide variety
of applications.
The LTC1744 is perfect for demanding communications
applications with AC performance that includes 77dB
SNR and 87dB spurious free dynamic range. Ultralow jitter
of 0.3ps_RMS allows undersampling of IF frequencies with
excellent noise performance. DC specs include ±4LSB
maximum INL and no missing codes over temperature.
The digital interface is compatible with 5V, 3V and 2V logic
systems. The ENC and ENC inputs may be driven differen-
tially from PECL, GTL and other low swing logic families or
from single-ended TTL or CMOS. The low noise, high gain
ENC and ENC inputs may also be driven by a sinusoidal
signal without degrading performance. A separate output
power supply can be operated from 0.5V to 5V, making it
easy to connect directly to any low voltage DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
BLOCK DIAGRA
A_IN+
±1V
DIFFERENTIAL
ANALOG INPUT _AIN–
SENSE
RANGE
SELECT
V_CM
4.7µF
2.5V_REF
50Msps, 14-Bit ADC with a ±1V Differential Input Range
S/H
CIRCUIT
14-BIT
PIPELINED ADC
CORRECTION
LOGIC AND
14
OUTPUT
SHIFT
LATCHES
REGISTER
OV_DD
0.1µF
OF
•••
D13
D0
CLKOUT
OGND
0.5V TO 5V
0.1µF
BUFFER
DIFF AMP
V_DD
5V
1µF
1µF
1µF
GND
CONTROL LOGIC
REFLB REFHA
4.7µF
0.1µF
1µF
REFLA REFHB ENC ENC MSBINV
0.1µF
1µF
DIFFERENTIAL
ENCODE INPUT
1744 BD
OE
1744f
1