LTC1663 Datasheet, PDF (1/12 Pages) Linear Technology – 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface

LTC1663
10-Bit Rail-to-Rail
Micropower DAC with 2-Wire Interface
FEATURES
s _{Micropower 10-Bit DAC in SOT-23}
s _{Low Operating Current: 60µA}
s _{Ultralow Power Shutdown Mode: 10µA}
s _{2-Wire Serial Interface Compatible}
with SMBus and I²C^TM
s _{Single 2.7V to 5.5V Operation}
s _{Selectable Internal Reference or Ratiometric to VCC}
s _{Buffered True Rail-to-Rail Voltage Output}
s _{Maximum DNL Error: 0.75LSB}
s _{Power-On Reset}
s _{8 User Selectable Addresses (MSOP Package)}
s _{0.6V VIL and 1.4V VIH for SDA and SCL}
s _{Small 5-Lead SOT-23 and 8-Lead MSOP Packages}
U
APPLICATIO S
s _{Digital Calibration}
s _{Offset/Gain Adjustment}
s _{Industrial Process Control}
s _{Automatic Test Equipment}
s _{Arbitrary Function Generators}
s _{Battery-Powered Data Conversion Products}
DESCRIPTIO
The LTC^®1663 is a 10-bit voltage output DAC with true
buffered rail-to-rail output voltage capability. It operates
from a single supply with a range of 2.7V to 5.5V. The
reference for the DAC is selectable between the supply
voltage or an internal bandgap reference. Selecting the
internal bandgap reference will set the full-scale output
voltage range to 2.5V. Selecting the supply as the refer-
ence sets the output voltage range to the supply voltage.
The part features a simple 2-wire serial interface compat-
ible with SMBus and I²C that allows communication
between many devices. The internal data registers are
double buffered to allow for simultaneous update of
several devices at once. The DAC can be put in low current
power-down mode for use in power conscious systems.
Power-on reset ensures the DAC output is at 0V when
power is initially applied, and all internal registers are
cleared.
, LTC and LT are registered trademarks of Linear Technology Corporation.
I²C is a trademark of Philips Electronics N.V.
BLOCK DIAGRA
4 (5)
V_CC
1.25V
BANDGAP
REFERENCE
REFERENCE
SELECT
10-BIT
DAC LATCH
MSOP
PACKAGE
ONLY
(6) AD0
(2) AD1
(3) AD2
COMMAND
LATCH
INPUT
LATCH
2-WIRE INTERFACE
SDA
SCL
1 (1)
5 (4)
NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE
+
–
R
R
GND
2 (7)
V_OUT 3 (8)
1663 BD
Differential Nonlinearity (DNL)
1.0
0.8
V_REF = V_CC = 5V
T_A = 25°C
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
0
28 156 384 512 640 768 896 1024
CODE
1663 G02
1