LTC1654 Datasheet, PDF (1/12 Pages) Linear Technology – Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package

FEATURES
s _{14-Bit Monotonic Over Temperature}
s _{Individually Programmable Speed/Power:}
3.5µs Settling Time at 750µA
8µs Settling Time at 450µA
s _{Maximum Update Rate: 0.9MHz}
s _{Smallest Dual 14-Bit DAC: 16-Lead Narrow}
SSOP Package
s _{Buffered True Rail-to-Rail Voltage Outputs}
s _{3V to 5V Single Supply Operation}
s _{User Selectable Gain}
s _{Power-On Reset and Clear Function}
s _{Schmitt Trigger On Clock Input Allows Direct}
Optocoupler Interface
U
APPLICATIO S
s _{Digital Calibration}
s _{Industrial Process Control}
s _{Automatic Test Equipment}
s _{Offset/Gain Adjustment}
Final Electrical Specifications
LTC1654
Dual 14-Bit Rail-to-Rail DAC
in 16-Lead SSOP Package
DESCRIPTIO
April 2000
The LTC^®1654 is a dual, rail-to-rail voltage output, 14-bit
digital-to-analog converter (DAC). It is available in a
16-lead narrow SSOP package, making it the smallest dual
14-bit DAC available. It includes output buffer amplifiers
and a flexible serial interface.
The LTC1654 has REFHI pins for each DAC that can be
driven up to V_CC. The output will swing from 0V to V_CC in
gain of 1 configuration or V_CC/2 in gain of 1/2 configura-
tion. It operates from a single 2.7V to 5.5V supply.
The LTC1654 has two programmable speeds: a FAST and
SLOW mode with ±1LSB settling times of 3.5µs or 8µs
respectively and supply currents of 750µA and 450µA in
the two modes. The LTC1654 also has shutdown capabil-
ity, power-on reset and clear function to 0V.
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRA
CS/LD
SCK
CONTROL
LOGIC
SDI
INPUT
LATCH
DAC
REGISTER
DAC B
+
–
32-BIT
SHIFT
REGISTER
REFHI B
V_{OUT B}
X₁/X_1/2 B
REFHI A
INPUT
LATCH
DAC
REGISTER
DAC A
+
V_{OUT A}
SDO
–
CLR
POWER-ON
RESET
REFLO B
REFLO A
X₁/X_1/2 A
1654 BD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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