LTC1403_15 Datasheet, PDF (1/20 Pages) Linear Technology – Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown

LTC1403/LTC1403A
Serial 12-Bit/14-Bit, 2.8Msps
Sampling ADCs with Shutdown
FEATURES
■ _{2.8Msps Conversion Rate}
■ _{Low Power Dissipation: 14mW}
■ _{3V Single Supply Operation}
■ _{–40°C to 125°C Guaranteed Operation}
■ _{2.5V Internal Bandgap Reference can be Overdriven}
■ _{3-Wire Serial Interface}
■ _{Sleep (10μW) Shutdown Mode}
■ _{Nap (3mW) Shutdown Mode}
■ _{80dB Common Mode Rejection}
■ _{0V to 2.5V Unipolar Input Range}
■ _{Tiny 10-Lead MS Package}
APPLICATIONS
■ _Automotive
■ _{Communications}
■ _{Data Acquisition Systems}
■ _{Uninterrupted Power Supplies}
■ _{Multiphase Motor Control}
■ _{Multiplexed Data Acquisition}
DESCRIPTION
The LTC^®1403/LTC1403A are 12-bit/14-bit, 2.8Msps se-
rial ADCs with differential inputs. The devices draw only
4.7mA from a single 3V supply and come in a tiny 10-lead
MS package. A Sleep shutdown feature lowers power
consumption to 10μW. The combination of speed, low
power and tiny package makes the LTC1403/LTC1403A
suitable for high speed, portable applications.
The 80dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 0V to 2.5V unipolar inputs differentially.
The absolute voltage swing for +A_IN and –A_IN extends from
ground to the supply voltage.
The serial interface sends out the conversion results during
the 16 clock cycles following CONV↑ for compatibility with
standard serial interfaces. If two additional clock cycles
for acquisition time are allowed after the data stream in
between conversions, the full sampling rate of 2.8Msps
can be achieved with a 50.4MHz clock.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
BLOCK DIAGRAM
10μF 3V
A_IN+
A_IN–
10μF
LTC1403A
7 _VDD
1+
S&H
2–
14-BIT ADC
14
V_REF
3
GND
4
2.5V
REFERENCE
5
6
11
EXPOSED PAD
THREE-
STATE
SERIAL
OUTPUT
PORT
8 SDO
TIMING
LOGIC
10 CONV
9 SCK
1403A TA01
–44
–50
–56
–62
–68
–74
–80
–86
–92
–98
–104
0.1
2nd, 3rd and SFDR vs
Input Frequency
THD 2nd, SFDR
3rd
1
10
FREQUENCY (MHz)
100
1403A TA02
1403fb
1