LTC1283_15 Datasheet, PDF (1/24 Pages) Linear Technology – 3V Single Chip 10-Bit Data Acquisition System

FEATURES
■ _{Single Supply 3.3V or ±3.3V Operation}
■ _{Software Programmable Features:}
Unipolar/Bipolar Conversions
4 Differential/8 Single-Ended Inputs
MSB- or LSB-First Data Sequence
Variable Data Word Length
■ _{Built-In Sample-and-Hold}
■ _{Direct 4-Wire Interface to Most MPU Serial Ports}
and all MPU Parallel Ports
■ _{15kHz Maximum Throughput Rate}
KEY SPECIFICATIO S
■ _{Minimum Guaranteed Supply Voltage: 3V}
■ _{Resolution: 10 Bits}
■ _{Offset Error: ±0.5LSB Max}
■ _{Linearity Error: ±0.5LSB Max}
■ _{Gain Error (LTC1283A): ±1LSB Max}
■ _{Conversion Time: 44μs}
■ _{Supply Current: 350μA Max, 150μA Typ}
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATI
4.7μF
3V
FOR 83CL410 CODE SEE
APPLICATIONS INFORMATION SECTION
LTC1283
DIFFERENTIAL
INPUT
MPU
(e.g., 83CL410)
3V
–3V
3V
T
BIPOLAR
INPUT
D_OUT
P1.1
D_IN
P1.2
SCLK
P1.3
UNIPOLAR
INPUTS
CS
P1.4
SERIAL DATA LINK
(+)
(–)
–UNIPOLAR
INPUT
–3V
LTC1283 • TA01
LTC1283
3V Single Chip 10-Bit Data
Acquisition System
DESCRIPTIO
The LTC1283 is a 3V data acquisition component which
contains a serial I/O successive approximation A/D con-
verter. It uses LTCMOS^TM switched capacitor technology
to perform either 10-bit unipolar, or 9-bit plus sign bipolar
A/D conversions. The 8-channel input multiplexer can be
configured for either single-ended or differential inputs (or
combinations thereof). An on-chip sample-and-hold is
included for all single-ended input channels.
The serial I/O is designed to be compatible with industry-
standard full-duplex serial interfaces. It allows either MSB-
or LSB-first data and automatically provides 2’s comple-
ment output coding in the bipolar mode. The output data
word can be programmed for a length of 8-, 10-, 12-, or
16-bit. This allows easy interface to shift registers and a
variety of processors.
Both the LTC1283A and LTC1283 are specified with offset
and linearity errors less than ±0.5LSB. The LTC1283A has
a gain error limit of ±1LSB. The 1283 is specified with a
gain error limit of ±2LSB for applications where gain is
adjustable or less critcial.
1.0
0.5
0
–0.5
– 1.0
0
Linearity Plot
512
OUTPUT CODE
1024
LTC1283 • TA02
1283fb
1