DC1682B Datasheet, PDF (8/26 Pages) Linear Dimensions Semiconductor – 12-port Type 2 power sourcing equipment (PSE) composed of a DC1682B daughter card and DC1680A mother board.

DEMO MANUAL DC1840B
Demonstration Circuit 1682B Operation
AUTO and MID Jumpers
Surge Protection
The AUTO and MID pins of the LTC4271 are set by
jumpers JP1 and JP2 respectively on the DC1682B
(Figure 10). Setting JP1 to HI enables the AUTO pin mode
in the LTC4270/LTC4271 chipset. J2 provides test points
for access to AUTO and MID.
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components,
as shown in Figure 11, are required at the main supply,
at the LTC4270 supply pins and at each port.
In AUTO pin mode (JP1 high), the LTC4270/LTC4271
chipset internal I²C registers default to the AUTO pin high
state after a software or hardware reset, or system power
on. The LTC4270/71 chipset autonomously detects, pow-
ers on and disconnects power to PDs without the need
for I²C host control.
Setting JP1 to LO disables AUTO pin mode and sets the
LTC4270/LTC4271 chipset to a low current shutdown
mode. An I²C host controller can then be used to con-
figure the LTC4270/LTC4271 chipset to semi-auto mode
for controlled PSE operation or to manual mode for test
purposes.
Setting JP2 to HI enables the midspan mode detection
backoff timer in the LTC4270/LTC4271 chipset. For end-
point PSEs, set JP2 to LO to disable midspan mode.
For quick PSE evaluation in AUTO pin mode with
MIDSPAN disabled, set JP1 HI and JP2 LO on the DC1682B.
Bulk transient voltage suppression (TVS_BULK) and bulk
capacitance (C_BULK) are required across the main PoE
supply and should be sized to accommodate system level
surge requirements.
Each LTC4270 requires a 10Ω, 0805 resistor (R1) in series
from supply AGND to the LTC4270 AGND pin. Across the
LTC4270 AGND pin and V_EE pin are an SMAJ58A, 58V
TVS (D1) and a 1μF, 100V bypass capacitor (C19). These
components must be placed close to the LTC4270 pins.
Finally, each port requires a pair of S1B clamp diodes:
one from OUTn to supply AGND and one from OUTn to
supply V_EE. The diodes at the ports steer harmful surges
into the supply rails where they are absorbed by the surge
suppressors and the V_EE bypass capacitance. The layout
of these paths must be low impedance. These S1B diodes
are placed on the DC1680 mother board of the DC1840 kit.
R35
10Ω
C19
1µF
100V
V_EE
AGND
D1
SMAJ58A
V_EE
LTC4270
VSSK SENSEn GATEn OUTn
C26
0.1µF
D26
B1100 RSENSEn
Qn
FDMC3612
34-PIN
CONNECTOR
DC1682B SIDE
DC1680 SIDE
Cn
0.22µF
X7R
100V
OUTn
S1B
PROTECTION
S1B
OUTn ⁺
TO
C_BULK
PORT
S1B
TVS_BULK
4 × 1.00
V_EE
V_EE
DC1840B F11
Figure 11. DC1682B, 1 of 12 Ports Surge Protection
8
dc1840bfc