LTC2258-14 Datasheet, PDF (6/32 Pages) Linear Technology – 14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs

LTC2258-14
LTC2257-14/LTC2256-14
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 9)
LTC2258-14
LTC2257-14
LTC2256-14
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
V_DD
OV_DD
I_VDD
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
DC Input
Sine Wave Input
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
l 1.1
1.9 1.1
1.9 1.1
1.9
V
l
44.7 83.2
45.3
27 69.1
27.9
19.5 58.1 mA
19.9
mA
I_OVDD
P_DISS
Digital Supply Current
Power Dissipation
LVDS Output Mode
Sine Wave Input, OV_DD=1.2V
DC Input
l
Sine Wave Input, OV_DD=1.2V
2.6
80.5 150
84.7
1.6
48.6 125
52.1
1.1
mA
35.1 105 mW
37.1
mW
V_DD
Analog Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
OV_DD Output Supply Voltage (Note 10)
l 1.7
1.9 1.7
1.9 1.7
1.9
V
I_VDD
Analog Supply Current Sine Wave Input
l
48.9 89
31.4 74.8
23.5 63.5 mA
I_OVDD Digital Supply Current Sine Input, 1.75mA Mode l
(0V_DD = 1.8V)
Sine Input, 3.5mA Mode
l
23.8 26
39.8 47.8
23.5 26
38.9 47.8
23.7 26
mA
39.5 47.8 mA
P_DISS Power Dissipation
Sine Input, 1.75mA Mode l
Sine Input, 3.5mA Mode
l
130.9 207
159.7 246
98.8 182
126.5 221
85 161 mW
113.4 201 mW
All Output Modes
P_SLEEP Sleep Mode Power
0.5
0.5
0.5
mW
P_NAP Nap Mode Power
9
9
9
mW
P_DIFFCLK Power Increase with Differential Encode Mode Enabled
10
10
10
mW
(No increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T_A = 25°C. (Note 5)
LTC2258-14
LTC2257-14
LTC2256-14
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
f_S
Sampling Frequency (Note 10)
l1
65 1
40 1
25 MHz
t_L
ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 4.52 12.5 500 19 20 500
ns
Duty Cycle Stabilizer On l 2.0 7.69 500 2.00 12.5 500 2.00 20 500
ns
t_H
ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 4.52 12.5 500 19 20 500
ns
Duty Cycle Stabilizer On l 2.0 7.69 500 2.00 12.5 500 2.00 20 500
ns
t_AP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
SYMBOL PARAMETER
CONDITIONS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
t_D
t_C
t_SKEW
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C_L = 5pF (Note 8)
C_L = 5pF (Note 8)
t_D – t_C (Note 8)
Full Data Rate Mode
Double Data Rate Mode
MIN
TYP
MAX
UNITS
l
1.1
1.7
3.1
ns
l
1
1.4
2.6
ns
l
0
0.3
0.6
ns
5.0
Cycles
5.5
Cycles
225814p
6