LTC3703IGN Datasheet, PDF (25/34 Pages) Linear Integrated Systems – 100V Synchronous Switching Regulator

LTC3703
Applications Information
MODE/SYNC Pin (External Synchronization)
The internal LTC3703 oscillator can be synchronized to
an external oscillator by applying and clocking the MODE/
SYNC pin with a signal above 2V_P-P . The internal oscillator
locks to the external clock after the second clock transition
is received. When external synchronization is detected,
LTC3703 will operate in forced continuous mode. If an
external clock transition is not detected for three suc-
cessive periods, the internal oscillator will revert to the
frequency programmed by the R_SET resistor. The internal
oscillator can synchronize to frequencies between 100kHz
and 600kHz, independent of the frequency programmed by
the R_SET resistor. However, it is recommended that an R_SET
resistor be chosen such that the frequency programmed
by the R_SET resistor is close to the expected frequency of
the external clock. In this way, the best converter operation
(ripple, component stress, etc) is achieved if the external
clock signal is lost.
Fault Conditions: Output Overvoltage Protection
(Crowbar)
The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the regula-
tor rises much higher than nominal levels. This condition
causes huge currents to flow, much greater than in normal
operation. This feature is designed to protect against a
shorted top MOSFET; it does not protect against a failure
of the controller itself.
The comparator (MAX in the Functional Diagram) detects
overvoltage faults greater than 5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the 0V condition persists; if V_OUT returns to a safe
level, normal operation automatically resumes.
Minimum On-Time Considerations (Buck Mode)
Minimum on-time t_ON(MIN) is the smallest amount of time
that the LTC3703 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays
and the amount of gate charge required to turn on the
top MOSFET. Low duty cycle applications may approach
this minimum on-time limit and care should be taken to
ensure that:
t_ON
=
V_OUT
V_IN • f
>
t_ON(MIN)
where t_ON(MIN) is typically 200ns.
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3703 will begin to skip
cycles. The output will be regulated, but the ripple current
and ripple voltage will increase. If lower frequency opera-
tion is acceptable, the on-time can be increased above
t_ON(MIN) for the same step-down ratio.
Pin Clearance/Creepage Considerations
The LTC3703 is available in two packages (GN16 and G28)
both with identical functionality. The GN16 package gives
the smallest size solution, however the 0.013" (minimum)
space between pins may not provide sufficient PC board
trace clearance between high and low voltage pins in higher
voltage applications. Where clearance is an issue, the G28
package should be used. The G28 package has four un-
connected pins between the all adjacent high voltage and
low voltage pins, providing 5(0.0106") = 0.053" clearance
which will be sufficient for most applications up to 100V.
For more information, refer to the printed circuit board
design standards described in IPC-2221 (www.ipc.org).
Efficiency Considerations
The efficiency of a switching regulator is equal to the out-
put power divided by the input power (x100%). Percent
efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power. It is often useful to analyze the individual
losses to determine what is limiting the efficiency and
what change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3703 circuits: 1) LTC3703 V_CC current, 2)
MOSFET gate current, 3) I²R losses, 4) Topside MOSFET
transition losses.
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