LTM8033 Datasheet, PDF (16/24 Pages) Linear Technology – Ultralow Noise EMC 36VIN, 3A DC/DC μModule Regulator

LTM8033
APPLICATIONS INFORMATION
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8033. The LTM8033 is neverthe-
less a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 4
for a suggested layout. Ensure that the grounding and
heat sinking are acceptable.
A few rules to keep in mind are:
1. Place the R_ADJ and R_T resistors as close as possible to
their respective pins.
2. Place the C_IN and C_FIN capacitors as close as possible
to the V_IN, FIN and GND connections of the LTM8033.
A haphazardly placed C_FIN capacitor may impair EMI
performance.
3. Place the C_OUT capacitors as close as possible to the
V_OUT and GND connection of the LTM8033.
4. Place the C_IN, C_FIN and C_OUT capacitors such that their
ground currents flow directly adjacent or underneath
the LTM8033.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8033.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 4. The LTM8033 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
PG SYNC
GND
RUN/SS
FIN
R_ADJ
R_T
SHARE
GND
C_FIN
BIAS
LTM8033
AUX
C_OUT
C_IN
V_OUT
GND
V_IN
THERMAL VIAS TO GND
Figure 4. Layout Showing Suggested External
Components, GND Plane and Thermal Vias
8033f
16