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LTC3445 Datasheet, PDF (11/24 Pages) Linear Technology – I2C Controllable Buck Regulator with Two LDOs in a 4mm × 4mm QFN
WU
W
TI I G DIAGRA
SDA
tLOW
tSU(DAT)
SCL
tHD(STA)
START
CONDITION
tHIGH
tr
tf
tHD(DAT)
tSU(STA)
tHD(STA)
REPEATED START
CONDITION
LTC3445
tBUF
tSUSTO
3445 TD
STOP
START
CONDITION CONDITION
I2C Fast Mode Timing Specifications (for Reference)
SYMBOL
fI2C(MAX)
tBUF
tHD(RSTA)
tSU(RSTA)
tSU(STOP)
tHD(DAT)
tSU(DAT)
tLOW
tHIGH
tSP
tf
PARAMETER
Maximum I2C Operating Frequency
Bus Free Time Between Stop and Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Clock Low Period
Clock High Period
Pulse Width of Spikes Suppressed by Input Filter
Clock, Data Fall Time (Note 1)
tr
Clock, Data Rise Time (Note 1)
Note 1: CB = Capacitance of one bus line.
MIN TYP MAX
0
400
1.3
0.6
0.6
0.6
0
0.9
100
1.3
0.6
0
50
20 + 0.1
300
• CB
20 + 0.1
300
• CB
UNITS
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
U
OPERATIO (refer to Figure 1)
BUCK REGULATOR
Main Control Loop
The LTC3445 uses a constant or spread spectrum fre-
quency, current mode step-down architecture (Figure 2).
Both the main (P-channel MOSFET) and synchronous
(N-channel MOSFET) switches are internal. During normal
operation, the internal top power MOSFET is turned on
each cycle when the oscillator sets the RS latch, and
turned off when the current comparator, ICOMP, resets the
RS latch. The peak inductor current at which ICOMP resets
the RS latch is controlled by the output of error amplifier
EA. When the load current increases, it causes a slight
decrease in the feedback voltage, FB, relative to an internal
reference voltage, which in turn, causes the EA’s output
voltage to increase until the average inductor current
matches the new load current. While the top MOSFET is
off, the bottom MOSFET is turned on until either the
inductor current starts to reverse, as indicated by the
current reversal comparator IRCMP, or the beginning of the
next clock cycle.
3445fa
11