DS26900 Datasheet, PDF (2/49 Pages) Maxim Integrated Products – JTAG Multiplexer/Switch

__________________________________________________________________________________________ DS26900
Table of Contents
1. BLOCK DIAGRAM ........................................................................................................................ 6
2. PIN DESCRIPTIONS ..................................................................................................................... 7
3. FUNCTIONAL DESCRIPTION .................................................................................................... 19
4. DETAILED DESCRIPTION.......................................................................................................... 20
4.1 MODES OF OPERATION............................................................................................................... 20
4.1.1 Single-Package Mode ..................................................................................................................... 20
4.1.2 Cascade Configuration Modes ........................................................................................................ 21
4.1.3 Deselect Mode and Redundancy..................................................................................................... 22
4.2 MASTER ARBITRATION ................................................................................................................ 23
4.2.1 Missing Test Master or Unused Test Master Port ............................................................................ 24
4.2.2 Detection of the Presence of Secondary Ports................................................................................. 24
4.2.3 Selection of the Secondary Port ...................................................................................................... 24
4.2.4 Master Port/Secondary Port Path Timing Description ...................................................................... 24
4.3 GPIO PINS—GENERAL-PURPOSE I/O ......................................................................................... 25
4.4 PROGRAMMABLE PULLUP/PULLDOWN RESISTORS........................................................................ 25
4.5 SIGNAL PATH CONFIGURATION—INVERSIONS .............................................................................. 25
4.6 SWITCH CONFIGURATION BY EXTERNAL TEST MASTER................................................................. 25
4.7 SWITCH CONFIGURATION BY TEST MASTER 1 OR TEST MASTER 2................................................. 26
5. RESETS ...................................................................................................................................... 27
5.1 GLOBAL RESET USAGE............................................................................................................... 27
5.2 SECONDARY PORT RESETS ........................................................................................................ 27
6. CONFIGURATION MODE ........................................................................................................... 28
6.1 SWITCH TAP CONTROLLER......................................................................................................... 28
6.1.1 Switch Instructions .......................................................................................................................... 28
7. DEVICE REGISTERS.................................................................................................................. 31
8. ADDITIONAL APPLICATION INFORMATION............................................................................ 37
8.1 ACCESSING INDIVIDUAL DEVICE JTAG ON A BOARD ..................................................................... 37
8.2 USING LED INDICATORS ON THE SSPI, ACT AND MCI PINS .......................................................... 37
8.3 USING 2.7V AND 1.8V LOGIC LEVELS WITH THE DS26900 ............................................................ 37
8.4 SERIES TERMINATION RESISTORS ............................................................................................... 37
9. PERIPHERY JTAG...................................................................................................................... 38
9.1 PERIPHERY JTAG DESCRIPTION ................................................................................................. 38
9.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................. 39
9.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS...................................................................... 41
9.3.1 SAMPLE/PRELOAD ....................................................................................................................... 41
9.3.2 EXTEST ......................................................................................................................................... 41
9.3.3 BYPASS ......................................................................................................................................... 41
9.3.4 IDCODE ......................................................................................................................................... 41
9.3.5 HIGHZ ............................................................................................................................................ 41
9.3.6 CLAMP ........................................................................................................................................... 42
9.4 JTAG TEST REGISTERS.............................................................................................................. 42
9.4.1 Bypass Register.............................................................................................................................. 42
9.4.2 Identification Register...................................................................................................................... 42
9.4.3 Boundary Scan Register ................................................................................................................. 42
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