SE8205 Datasheet, PDF (7/9 Pages) Shanghai Leiditech Electronic Technology Co., Ltd – Thyristor Surge Suppressors

Thyristor Surge Suppressors
P0060~P3500SA_B_C Series
Soldering Parameters
Figure 5. Test circuit 3 for dynamic I_H parameter
Pb-Free assembly
R
(see Fig. 1)
Pre Heat
-Temperature Min (T ) _s(min)
-Temperature Max (T ) _s(max)
-Time (Min to Max) (t _s)
60-180 secs.
Average ramp up_Vr_Ba_At_Te ₌(L_- iq₄u₈id_VusTemp (T _L)
to peak)
3°C/sec^D. M^.Ua^.Tx.
Surg_Te_Pgenerator
T_L
T_S(max)
Figure 1
Ramp-up
T_S(max) to T_L - Ramp-up Rate
-Temperature (T _L) (Liquidus)
-Temperature (t _L)
3°C/sec. Max.
60-150 secs.
T_S(min)
Preheat
t_S
Peak Temp (T_P)
25
Time
within 5°C of
This is a
actual PeakTemp (t _p)
GO-NOGO test which
30 secs. Max.
allows to confirm the
holding
current
(I_H)
level
time to
in a^(t
peak
2 5ºC
temperature
to peak)
Ramp-downfuRnactteional _{test circuit.}
6°C/sec. Max.
Time 2 5°C to PeakTemp (T _P)
8 min. Max.
Do not exce_Te_Ed_{ST PROCEDURE}
1/ Adjust the current level at the Iv Halue by short circuiting the AK of the D.U.T.
2/ Fire the D.U.T.w ith a surge current
I=PP 10A, 10/1000µs.
3/ The D.U.T.w ill come back off-state within 50ms maximum.
t_P
Critical Zone
TL to T P
t_L
Ramp-down
Time
Lead Material
Terminal Finish
Body Material
Copper Alloy
100% Matte-Tin Plated
High Temp Voltage
Blocking
80% Rated V_DRM (V_AC Peak
504 or 1008 hrs. MIL-STD-750 (Method 1040)
JEDEC, JESD22-A-101
Temp Cycling
Biased Temp &
Humidity
High Temp Storage
Low Temp Storage
cycles. MIL-STD-750 (Method 1051) EIA/JEDEC,
JESD22-A104
52 V_DC
JEDEC, JESD22-A-101
JEDEC, JESD22-A-101
-65°C, 1008 hrs.
Thermal Shock
Autoclave (Pressure
Cooker Test)
Resistance to Solder
Heat
Moisture Sensitivity
Level
10 cycles. MIL-STD-750 (Method 1056) JEDEC,
JESD22-A-106
JEDEC, JESD22-A-102
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