ISPLSI1016E_02 Datasheet, PDF (9/12 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1016E
Maximum GRP Delay vs GLB Loads
3
ispLSI 1016E-80
ispLSI 1016E-100
2
1
1
Power Consumption
4
ispLSI 1016E-125
IGNS ₈
12
16
DES ^{GLB Load}
16E GRP/GLB.eps
Power consumption in the ispLSI 1016E device depends Figure 3 shows the relationship between power and
W on two primary factors: the speed at which the device is operating speed.
operating and the number of Product Terms used.
NE ^{Figure 3. Typical Device Power Consumption vs fmax}
130
R _{ispLSI 1016E}
120
FO ₁₁₀
A 100
E ₉₀
16 ₈₀
10_{0 20 40 60 80 100 120 140}
I _{fmax (MHz)}
S _{Notes: Configuration of four 16-bit counters}
Typical current at 5V, 25°C
pL _{ICC can be estimated for the ispLSI 1016E using the following equation:}
is ICC(mA) = 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004)
Where:
E _{# of PTs = Number of product terms used in design}
S# of nets = Number of signals used in device
U^{Max freq = Highest clock frequency to the device (in MHz)}
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads
on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the
value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127B-16-80-isp/1016
9