2032VL Datasheet, PDF (9/12 Pages) Lattice Semiconductor – 2.5V In-System Programmable SuperFAST™ High Density PLD

Specifications ispLSI 2032VL
Signal Descriptions
Signal Name
GOE 0
Y0
RESET/Y1
BSCAN
TDI/IN 0
TMS/NC¹
TDO/IN 1
TCK/Y2
GND
VCC
NC¹
I/O
Description
Global Output Enable Pin
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the
device.
This pin performs two functions: (1) Dedicated clock input. This clock input is brought into the Clock
Distribution Network and can optionally be routed to any GLB and/or I/O cell on the device. (2) Active
Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
Input – Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
Input – This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load
programming data into the device. When BSCAN is high, it functions as a dedicated input pin.
Input – When BSCAN is logic low, this pin functions as a mode control pin for the Boundary Scan State
Machine.
Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin
pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the
Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is
brought into the Clock Distribution Network and can optionally be routed to any GLB.
Ground (GND)
Vcc
No Connect
Input/Output pins – These are the general purpose I/O pins used by the logic array.
Signal Locations
Signal
GOE 0
Y0
RESET/Y1
BSCAN
TDI/IN 0
TMS/NC¹
TDO/IN 1
TCK/Y2
GND
VCC
NC¹
44-Pin TQFP
40
5
29
7
8
30
18
27
17, 39
6, 28
—
44-Pin PLCC
2
11
35
13
14
36
24
33
1, 23
12, 34
—
48-Pin TQFP
43
5
31
7
8
32
19
29
18, 42
6, 30
12, 24, 36, 48
49-Ball caBGA
A4
C1
D7
D1
E2
C6
G4
E7
C4, E4
D3, D5
A1, A7, D4, G1, G7
I/O Locations
Signal
44-Pin TQFP
44-Pin PLCC
I/O 0 - I/O 6 9, 10, 11, 12, 13, 14, 15 15, 16, 17, 18, 19, 20, 21
I/O 7 - I/O 13 16, 19, 20, 21, 22, 23, 24 22, 25, 26, 27, 28, 29, 30
I/O 14 - I/O 20 25, 26, 31, 32, 33, 34, 35 31, 32, 37, 38, 39, 40, 41
I/O 21 - I/O 27 36, 37, 38, 41, 42, 43, 44 42, 43, 44, 3, 4, 5, 6
I/O 28 - I/O 31 1, 2, 3, 4
7, 8, 9, 10
1. NC pins are not to be connected to any active signals, VCC or GND.
48-Pin TQFP
9, 10, 11, 13, 14, 15, 16
17, 20, 21, 22, 23, 25, 26
27, 28, 33, 34, 35, 37, 38
39, 40, 41, 44, 45, 46, 47
1, 2, 3, 4
49-Ball caBGA
E1, F2, F1, E3, F3, G2, F4
G3, F5, G5, F6, G6, E5, E6
F7, D6, C7, B6, B7, C5, B5
A6, B4, A5, B3, A3, B2, A2
C3, C2, B1, D2
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