160V Datasheet, PDF (5/37 Pages) Lattice Semiconductor – In-System Programmable 3.3V Generic Digital CrosspointTM

Specifications ispGDX160V/VA
Figure 3. Adjacent I/O Cells vs. Direct Input Path for
ispGDX160V/VA, I/O D23
I/O Group A
D21 MUX Out
I/O Group B
D22 MUX Out
I/O Group C
D24 MUX Out
I/O Group D
D25 MUX Out
ispGDX160V/VA I/O Cell
4x4
Crossbar
Switch
S1 S0
.m0
.m1
D23
.m2
.m3
It can be seen from Figure 3 that if the D21 adjacent I/O
cell is used, the I/O group “A” input is no longer available
as a direct MUX input.
The ispGDXV/VA can implement MUXes up to 16 bits
wide in a single level of logic, but care must be taken
when combining adjacent I/O cell outputs with direct
MUX inputs. Any particular combination of adjacent I/O
cells as MUX inputs will dictate what I/O groups (A, B, C
or D) can be routed to the remaining inputs. By properly
choosing the adjacent I/O cells, all of the MUX inputs can
be utilized.
Special Features
Slew Rate Control
All output buffers contain a programmable slew rate
control that provides software-selectable slew rate op-
tions.
Open Drain Control
All output buffers provide a programmable Open-Drain
option which allows the user to drive system level reset,
interrupt and enable/disable lines directly without the
need for an off-chip Open-Drain or Open-Collector buffer.
Wire-OR logic functions can be performed at the printed
circuit board level.
Pull-up Resistor
All pins have a programmable active pull-up. A typical
resistor value for the pull-up ranges from 50kΩ to 80kΩ.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds
the previously driven state when all drivers connected to
the pin (including the pin's output driver as well as any
other devices connected to the pin by external bus) are
tristated.
Table 2. Adjacent I/O Cells (Mapping of
ispGDX160V/VA)
Data A/ Data B/ Data C/ Data D/
MUXOUT MUXOUT MUXOUT MUXOUT
B20
B22
B21
B19
B18
B21
B23
B22
B20
B19
B22
B24
B23
B21
B20
Reflected ^B23
B25
B24
B22
B21
I/O Cells _D16
D18
D17
D15
D14
D17
D19
D18
D16
D15
D18
D20
D19
D17
D16
D19
D21
D20
D18
D17
D20
D18
D19
D21
D22
D21
D19
D20
D22
D23
D22
D20
D21
D23
D24
Normal _D23
D21
D22
D24
D25
I/O Cells
B16
B14
B15
B17
B18
B17
B15
B16
B18
B19
B18
B16
B17
B19
B20
B19
B17
B18
B20
B21
ispGDX160VA New Features
Unique to the ispGDX160VA are user-programmable
I/Os supporting either 3.3V or 2.5V output voltage level
options. The ispGDX160VA uses a VCCIO pin to provide
the 2.5V reference voltage when used. The ispGDX160VA
VCCIO pin occupies the same location as VCC on the
ispGDX160V, allowing drop-in replacement. The
ispGDX160VA offers improved performance by reducing
fanout delays and has PCI compatible drive capability.
Only the ispGDX160VA is available in the fastest (3.5ns)
Commercial speed grade and in -5,-7, and -9ns Industrial
grades in all packages.
The ispGDX160VA has a device ID different from the
ispGDX160V requiring that the latest Lattice download
software be used for programming and verification. Al-
though the ispGDX160VA and ispGDX160V are
functionally equivalent, they are not 100% JEDEC com-
patible. All design files must be recompiled targeting the
ispGDX160VA.
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