LC5256MC Datasheet, PDF (44/92 Pages) Lattice Semiconductor – 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXP sysCONFIG Port Timing Specifications
Symbol
Timing Parameter
sysCONFIG Write Cycle Timing
t_SUCS
Input setup time of CS to CCLK rise
t_HCS
Hold time of CS to CCLK rise
t_SUWD
Input setup time of write data to CCLK rise
t_HWD
Hold time of write data to CCLK rise
t_PRGM
Low time to reset device SRAM
t_DINIT
INIT delay time
t_IODISS
User I/O disable
t_IOENSS
User I/O enable
t_WH
Write clock High pulse width
t_WL
Write clock Low pulse width
f_MAXW
Write f_MAX
sysCONFIG Read Cycle Timing
t_HREAD
t_SUREAD
t_RH
t_RL
f_MAXR
t_CORD
Hold time of READ to CCLK rise
Input setup time of READ High to CCLK rise
READ clock high pulse width
READ clock low pulse width
Read f_MAX
Clock to out for read data
Min.
10
1
10
0
5
—
—
—
18
18
—
1
15
18
18
—
—
Max. Units
—
ns
—
ns
—
ns
—
ns
50
ns
5
ms
—
ns
—
ns
—
ns
—
ns
27
MHz
—
ns
—
ns
—
ns
—
ns
27
MHz
25
ns
44