LFSC Datasheet, PDF (42/237 Pages) Lattice Semiconductor – LatticeSC/M Family Data Sheet

Lattice Semiconductor
Architecture
LatticeSC/M Family Data Sheet
Figure 2-32. PowerPCI and MPI Schematic
PowerPC
TSZ[0:1]
RETRY
TEA
BURST
DP[0:m]
D[0:n]
A[14:31]
CLKOUT
RD/WR
TA
BDIP
IRQx
TS
LatticeSC FPGA
1, 2, 4
MPI_TSZ[0:1]
MPI_RTRY
MPI_TEA
MPI_BURST
DP[0:m]
8, 16, 32
D[0:n]
PPC_A[14:31]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BDIP
MPI_IRQ
MPI_STRB
CS0
CS1
DOUT
CCLK
DONE
INIT
HDC
LDC
To Daisy-
Chained
Devices
Bus
Controller
Configuration and Testing
The following section describes the configuration and testing features of the LatticeSC family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeSC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage V_CCJ and can
operate with LVCMOS33, 25 and 18 standards. For additional detail refer to technical information at the end of the
data sheet.
Device Configuration
All LatticeSC devices contain three possible ports that can be used for device configuration. The serial port, which
supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial configuration.
The MPI port supports 8-bit, 16-bit or 32-bit configuration.
The serial port supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System
Configuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins
and the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for gen-
eral purpose I/O. All I/Os for the sysCONFIG and MPI ports are in I/O bank #1.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a
configuration port is selected, that port is locked and another configuration port cannot be activated until the next
re-initialization sequence. For additional detail refer to technical information at the end of the data sheet.
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