ISPPAC-POWR604 Datasheet, PDF (4/29 Pages) Lattice Semiconductor – In-System Programmable Power Supply Sequencing Controller and Monitor

Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Pin Descriptions (Continued)
Number Name
Pin Type
Voltage Range
Description
42 NC
—
—
No Connect
43 NC
—
—
No Connect
44 NC
—
—
No Connect
1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on VDDINP.
2. The open-drain outputs can be powered independently of VDD and pulled up as high as +6.0V (referenced to ground). Exception, CLK pin
26 can only be pulled as high as VDD.
3. VDDINP can be chosen independent of V_DD. It applies only to the four logic inputs IN1-IN4.
4. The six VMON inputs can be biased independently of VDD. The six VMON inputs can be as high as 7.0V Max (referenced to ground).
5. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design time.
In output mode it is an open-drain type pin and requires an external pull-up resistor (pullup voltage must be ≤ V_DD). Multiple ispPAC-
POWR604 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked
by the master. The slave needs to be set up using the clock as an input.
6. RESET is an active low INPUT pin, external pull-up resistor required. When driven low it resets all internal PLD flip-flops to zero, and may
turn “ON” or “OFF” the output pins, depending on the polarity configuration of the outputs in the PLD. If a reset function is needed for the
other devices on the board, the PLD inputs and outputs can be used to generate these signals. The RESET connected to the POR pin can
be used if multiple ispPAC-POWR604 devices are cascaded together in expansion mode or if a manual reset button is needed to reset the
PLD logic to the initial state. While using the ispPAC-POWR604 in hot-swap applications it is recommended that either the RESET pin be
connected to the POR pin, or connect a capacitor to ground (such that the time constant is 10 ms with the pull-up resistor) from the RESET
pin.
7. The CREF pin requires a 0.1µF capacitor to ground, near the device pin. This reference is used internally by the device. No additional
external circuitry should be connected to this pin.
8. The four digital outputs (pins 12-15) are named OUT5-OUT8 to match ispPAC-POWR1208 pin names and to allow easy design migration.
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses above those listed values may cause permanent
damage to the device. Functional operation of the device at these or any other conditions above those indicated in
the operating sections of this specification is not implied.
Symbol
Parameter
Conditions
Min.
Max. Units
VDD
Core supply voltage at pin
—
-0.5
6.0
V
VDD_INP¹
V_IN²
VMON
V_TRI
Digital input supply voltage for IN1-IN4
Input voltage applied, digital inputs
Input voltage applied, V_MON voltage monitor inputs
Tristated or open drain output, external voltage applied
(CLK pin 26 pull-up ≤ VDD).
—
-0.5
6.0
V
—
-0.5
6.0
V
—
-0.5
7.0
V
—
-0.5
6.0
V
T_S
Storage temperature
—
-65
150
°C
T_A
Ambient temperature with power applied
—
-55
125
°C
T_SOL
Maximum soldering temperature (10 sec. at 1/16 in.)
—
—
260
°C
1. V_DDINP is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V_DDINP pin with appropriate
supply voltage for the given input logic range.
2. Digital inputs are tolerant up to 5.5V, independent of the V_DDINP voltage.
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