GAL6002 Datasheet, PDF (4/16 Pages) Lattice Semiconductor – High Performance E2CMOS FPLA Generic Array Logic

ILMC and IOLMC Configurations
ICLK
Specifications GAL6002
INPUT
or I/O
LATCH
E
Q
D
INVALID
REG.
Q
D
MUX
00
01
10
11
AND
ARRAY
LATCH(i) ISYN(i)
ILMC/IOLMC
Generic Logic Block Diagram
Input Macrocell JEDEC Fuse Numbers
INSYNC
8218
8220
8222
8224
8226
8228
8230
8232
8234
8236
INLATCH
8219
8221
8223
8225
8227
8229
8231
8233
8235
8237
ILMC
0
1
2
3
4
5
6
7
8
9
I/O Macrocell JEDEC Fuse Numbers
IOSYNC
8238
8240
8242
8244
8246
8248
8250
8252
8254
8256
IOLATCH
8239
8241
8243
8245
8247
8249
8251
8253
8255
8257
IOLMC
9
8
7
6
5
4
3
2
1
0
4