ISPGDX2VBC Datasheet, PDF (38/75 Pages) Lattice Semiconductor – ispGDX2™ Device Datasheet

Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters¹ (Continued)
Over Recommended Operating Conditions
-3
-32
-35
-5
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
t_OELSi
Latch Setup Time (Global Gate)
1.40 — 1.40 — 1.40 — 2.33 — ns
t_{OELSi_PT}
Latch Setup Time (Product Term Gate)
1.00 — 1.00 — 1.00 — 1.67 — ns
t_OESi
Register Setup Time (Global Clock)
1.00 — 1.00 — 1.40 — 2.33 — ns
t_{OESi_PT}
Register Setup Time (Product Term Clock) 1.00 — 1.00 — 1.00 — 1.67 — ns
S _tOESRPWi
Asynchronous Set/Reset Pulse Width
— 2.50 — 2.50 — 2.50 — 4.17 ns
Timing v.2.2
E ^{1. Internal parameters are not tested and are for reference only. Refer to the timing model in this data sheet for details.}
2. t_{PLL_DELAY} is the unit of increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to t_RANGE (as
SELDEICSTCODNETVIINCUED ^{given in the sysCLOCK PLL Timing section) in either direction in steps of size tPLL_DELAY.}
35