LFXP Datasheet, PDF(27/130 Page) Lattice Semiconductor

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LFXP Datasheet, PDF (27/130 Pages) Lattice Semiconductor – LatticeXP Family Data Sheet

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Lattice Semiconductor

Architecture

LatticeXP Family Data Sheet

Typical I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels.

After the POR signal is deactivated, the FPGA core logic becomes active. It is the userâs responsibility to ensure

that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of all the

I/O banks that are critical to the application. The default conï¬guration of the I/O pins in a blank device is tri-state

with a weak pull-up to VCCIO. The I/O pins will not take on the user conï¬guration until VCC, VCCAUX and VCCIO

have reached satisfactory levels at which time the I/Os will take on the user-conï¬gured settings.

The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buff-

ers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended

that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered up before or

together with the VCC and VCCAUX supplies.

Supported Standards

The LatticeXP sysIO buffer supports both single-ended and differential standards. Single-ended standards can be

further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5,

1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually conï¬gurable options for

drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other sin-

gle-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS,

LVPECL, differential SSTL and differential HSTL. Tables 2-7 and 2-8 show the I/O standards (together with their

supply and reference voltages) supported by the LatticeXP devices. For further information on utilizing the sysIO

buffer to support a variety of standards please see the details of additional technical documentation at the end of

this data sheet.

Table 2-7. Supported Input Standards

Input Standard

Single Ended Interfaces

VREF (Nom.)

LVTTL

LVCMOS332

LVCMOS252

LVCMOS18

LVCMOS15

LVCMOS122

PCI

HSTL18 Class I, II

0.9

HSTL18 Class III

1.08

HSTL15 Class I

0.75

HSTL15 Class III

0.9

SSTL3 Class I, II

1.5

SSTL2 Class I, II

1.25

SSTL18 Class I

0.9

Differential Interfaces

Differential SSTL18 Class I

Differential SSTL2 Class I, II

Differential SSTL3 Class I, II

Differential HSTL15 Class I, III

Differential HSTL18 Class I, II, III

LVDS, LVPECL

BLVDS

1. When not speciï¬ed VCCIO can be set anywhere in the valid operating range.

2. JTAG inputs do not have a ï¬xed threshold option and always follow VCCJ.

VCCIO1 (Nom.)

1.8

1.5

3.3

2-24

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