LFEC Datasheet, PDF (27/117 Pages) Lattice Semiconductor – LatticeECP/EC Family Data Sheet

Lattice Semiconductor
Figure 2-26. Input Register DDR Waveforms
DI
(In DDR Mode)
A
B
DQS
DQS
Delayed
D0
D2
Architecture
LatticeECP/EC Family Data Sheet
C
D
E
F
B
D
A
C
Figure 2-27. INDDRXB Primitive
D
ECLK
LSR
SCLK
CE
QA
IDDRXB
QB
DDRCLKPOL
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-28 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-29 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
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